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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com preliminary XRT86SH221 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu may 2007 rev. p1.0.5 general description the XRT86SH221 (voyager-lite) is a physical layer sdh to pdh mapper/demapper which enables e1 aggregation to stm-1 via standard vc-12 to au-3 and tug-3/au-4 mapping protocols. voyager-lite supports all the framing, mapping and grooming functions required for stm-1 mapper applications. the device generates and terminates all sdh regenerator section, multiplexer section and path overhead including the low-order virtual container (vc) path overhead. e1 framing is transparent; therefore, the device neither generates nor terminates the e1 frame. a single voyager-lite performs mapping of 21 asynchronous e1 spans to either vc-12/tu-12/tug- 2/ vc-3/au-3/stm-0 or vc-12/tu-12/tug-2/tug-3/ stm-0. mapping to stm-1 requires (3) voyager-lite devices with one acting as "master" framer and two acting as "slave" framers. in this configuration, voyager-lite performs all the necessary framing, pointer processing and mapping functions required for mapping of 63xe1 spans to either vc-12/tu-12/ tug-2/vc-3/au-3/stm-1 or vc-12/tu-12/tug-2/ tug-3/vc-4/au-4/stm-1 as shown in the block diagram. f igure 1. s implified b lock d iagram stm-1 soh processor jtag microprocessor stm-1 soh processor 21 ch e1 frame sync bit retimer 21 ch e1 short haul liu tx 21 ch e1 short haul liu rx vc-12 cross connect 21x21 rx vc-12 cross connect 21x21 tx vc-12 mapper + tu-12 pointer proc rx vc-12 mapper + tu-12 pointer proc tx XRT86SH221 voyager lite sdh path proc (poh) tu-12 to tug2 rx vc3/ au3 tug3/ vc4/ au4 tx sdh trans- port proc (soh) rx sdh trans- port proc (soh) tx telecom bus rx telecom bus tx pll e1, 2xe1 4xe1, 8xe1 8khz master slave 19.44mhz sdh oh drop sdh oh add single input clock reference jtag port microprocessor interface recovered line clock egress ingress telecom bus or serial port interface vc-4 poh drop vc-4 p oh add package ordering information p roduct n umber p ackage t ype o perating t emperature r ange XRT86SH221ib 388 pbga -40c to +85c
XRT86SH221 preliminary 2 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 features vt mapper maps up to 21 synchronous or asynchronous e1 signal s to sdh au-3 via tug-2 and tu-12, or to sdh stm-0 payload capacity via vt groups and vt2. dynamic vt/tu size selection. inserts valid v5 bit interleaved parity bip-2 in th e transmit direction. detects and counts v5 bip-2 errors for performance monitoring. configurable remote error indication rei-v insertio n for v5 bip-2 errors. supports proprietary v5 remote loopcodes. detects and counts remote errors. automatic receive monitor functions include vt/tu r emote defect indication rdi-v, vt/tu remote failure indication rfi-v, vt/tu remote error indication rei -v, bip-2 errors, vt/tu ais, vt/tu automatic protec tion switching (aps) signalling for low order path level , and vt/tu loss of pointer lop-v. automatic receive monitoring functions can be confi gured to provide an interrupt to the control system , or the device can be operated in a polled mode. test pattern generation and detection/dropping for setup and maintenance. user configurable for vt/tu label, ais-v, rdi-v, rf i-v, rei-v, aps, force bip-2 errors, or unequipped tributary insertion. e1 receive framing synchronizer provides a standard compliant 2.048 mbits pcm30 crc -4 e1 framer. provides off-line framer. complies with standards such as: itu-t g.703, g.70 4, g.706 (including annex b), g.732, g.735, g.736, g.737, g.761, g.823, i.431 and ets 300 011, 300 233 . supports fas, signaling multiframe, and crc-4 frami ng structure. fas reframe time is 625 m s maximum. provides loss of frame (lof), loss of multiframe de tection. provides change of frame alignment (cofa) detection . provides change of signaling multiframe alignment (comfa) detection. provides a 2-frame slip buffer for bit retiming.
preliminary XRT86SH221 3 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu sdh transmitter performs standard stm-0/stm-1 transmit processing. conforms to itu-t i.432, ansi t1.105, and bellcore- 253 provides a 51.84mhz stm-0 serial interface or 6mhz / 19mhz 8-bit stm-0 / stm-1 parallel interface. performs sdh frame insertion and accepts external f rame synchronization. performs optional transmit data scrambling. performs poh, sdh oh generation/insertion. generates transmit payload pointer (h1, h2) (fixed at 522) with ndf insertion. inserts a1/a2 with optional error mask. computes and inserts bip-8 (b1, b2) with optional e rror mask. generates ais-l, rei-l and rdi-l according to recei ver state with option of sw or hw insertion. inserts los, forces sef by software. generates rdi-p and rei-p automatically with option al sw or hw override. inserts fixed-stuff columns, calculates and inserts b3 error code. sdh receiver performs standard stm-0/stm-1 receive processing. conforms to itu-t i.432, ansi t1.105, and bellcore- 253. provides fully programmable threshold detection for sd and sf conditions. provides a 51.84mhz stm-0 serial interface or 6mhz / 19mhz 8-bit stm-0 / stm-1 parallel interface. provides section trace buffer with mismatch detecti on and invalid message detection. performs sdh frame synchronization. supports ndf, positive stuff and negative stuff for pointer processor. performs receive data de-scrambling. performs poh, sdh oh interpretation/extraction. interprets payload pointer (h1, h2). detects out of frame (oof), loss of frame (lof), lo ss of signal (los), aps failure. detects line alarm indication(l-ais), line remote d efect indication (l-rdi), loss of pointer. detects path alarm indication, path remote defect i ndication, path extended rdi. provides signal label monitor with plm detection. supports path trace buffer with tim-p and invalid m essage detection. computes and compares b3, rei-l and rei-p errors. computes and compares bip-8 (b1, b2) and counts the errors.
XRT86SH221 preliminary i sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 table of contents general description ................................ ................................................... ............. 1 f igure 1. s implified b lock d iagram ................................................... ................................................... ...................................... 1 p ackage o rdering i nformation ................................................... ................................................... 1 features ........................................... ................................................... .......................... 2 table of contents.................................. ................................................... ................. i 1.0 pin descriptions ............................... ................................................... .............................................. 4 1.1 microprocessor interface pins.................. ................................................... ....................................... 4 1.2 boundary scan and other test pins.............. ................................................... ................................... 6 1.3 general purpose input and output pins.......... ................................................... ............................... 7 1.4 timing and clock signals....................... ................................................... ................................................ 7 1.5 low speed line interface signals ............... ................................................... ...................................... 9 1.6 high speed serial interface.................... ................................................... ........................................... 12 1.7 high speed telecom bus interface.............. ................................................... ................................... 13 1.8 high speed section and path overhead bus ....... ................................................... ......................... 15 1.9 high speed tu poh overhead bus ................. ................................................... ..................................... 16 1.10 power and ground pins ......................... ................................................... ............................................. 18 2.0 applications and physical interface general ove rview............................................. 20 f igure 2. a pplication d iagram ................................................... ................................................... ............................................ 20 2.1 physical interface ............................. ................................................... ................................................... . 21 f igure 3. s implified b lock d iagram of the p hysical i nterface ................................................... .......................................... 21 2.2 telecom bus interface .......................... ................................................... ............................................... 22 f igure 4. s implified b lock d iagram of the t elecom b us i nterface ................................................... ................................... 22 2.3 stm-0 serial interface sdh frame synchronizatio n and timing interface....................... 23 f igure 5. s implified b lock d iagram of the s erial p ort i nterface ................................................... .................................... 23 2.4 sdh frame synchronization and timing interface . ................................................... .................. 24 f igure 6. s implified b lock d iagram of the sdh f rame s ynchronization ................................................... .......................... 24 2.5 sdh overhead add-drop interfaces ............... ................................................... ................................ 25 f igure 7. s implified b lock d iagram of the sdh o verhead a dd -d rop i nterface ................................................... .............. 25 2.6 e1 short haul line interface ................... ................................................... .......................................... 26 2.7 e1 timing interface ............................ ................................................... ................................................... .. 27 2.8 microprocessor interface ....................... ................................................... ......................................... 27 3.0 functional description ......................... ................................................... ................................... 28 f igure 8. f unctional b lock d iagram ................................................... ................................................... .................................. 28 3.1 ingress data path functional blocks ............ ................................................... .............................. 29 f igure 9. s implified b lock d iagram of the i ngress d ata p ath ................................................... ........................................... 29 3.2 e1 receive liu (rxe1liu) ....................... ................................................... ................................................... 29 3.3 transmit low-order (tu) overhead insertion bus (txtupoh) .......................................... ........ 29 3.4 vc-12/tu-12 transmit low-order mapper and overh ead processor (txlopohproc)...... 30 3.5 vc-12 transmit cross-connect (txvc12xc) ........ ................................................... ............................ 30 3.6 transmit sdh soh/poh insertion bus (txoh) ...... ................................................... ........................... 30 3.7 sdh transmit mapper and path overhead processor (txpohproc) ..................................... 3 1 3.8 sdh transmit framer and section overhead proces sor (txsohproc)............................... 32 3.9 transmit telecom bus (txtbus) .................. ................................................... ....................................... 33 3.10 egress data path functional blocks ............ ................................................... ............................. 34 f igure 10. s implified b lock d iagram of the e gress d ata p ath ................................................... ......................................... 34 3.11 receive telecom bus (rxtbus).................. ................................................... ........................................ 34 3.12 sdh receive framer and section overhead proces sor (rxsohproc) ............................... 35 3.13 sdh receive mapper and path overhead processor (rxpohproc) ..................................... 3 6 4.0 voyager-lite hardware architecture and algorith ms ............................................... 3 7 f igure 11. v oyager -l ite a rchitecture ................................................... ................................................... .............................. 37 4.1 multiplexing structure......................... ................................................... .............................................. 38 f igure 12. m ultiplexing structure ................................................... ................................................... .................................... 38 4.2 functional blocks .............................. ................................................... ................................................... 39 4.3 sdh transmit data flow ......................... ................................................... .............................................. 39 f igure 13. sdh t ransmitter g eneral s tructure ................................................... ................................................... ............. 40 4.4 sdh receive data flow.......................... ................................................... ................................................ 40 f igure 14. g eneral c omposition of a sdh stm-n r eceiver ................................................... .............................................. 41 4.5 vt mapper..................................... ................................................... ................................................... ........... 41
preliminary XRT86SH221 ii rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu f igure 15. t op l evel b lock d iagram ................................................... ................................................... .................................. 42 4.6 interrupts and status .......................... ................................................... ............................................... 43 f igure 16. i nterrupt h ierarchy ................................................... ................................................... ......................................... 43 4.7 interrupt processing and control ............... ................................................... ................................ 44 4.8 stm-0/1 receive transport processor............ ................................................... ............................... 44 f igure 17. byte_align b lock f unctional d iagram ................................................... ................................................... ........ 44 t able 1: 16- byte frame for t rail api d .................................................. ................................................... ................................ 49 f igure 18. r eceive t race b uffer m emory ................................................... ................................................... ......................... 50 t able 2: a ddressing s cheme u sed to a ccess the sdh oh b ytes .................................................. ...................................... 51 f igure 19. r eceive t ransport o verhead i nterface t iming ................................................... ................................................ 52 stm-0/1 receive path processor..................... ................................................... ......................... 53 f igure 20. p ointer p rocessing fsm ............................................... ................................................... ...................................... 55 t able 3: sdh p ointer e vent t ypes .................................................. ................................................... ..................................... 55 f igure 21. c oncatenated p ointer i ndicator p rocessing fsm............................................... ............................................... 57 t able 4: rdi-p s ettings and i nterpretation .................................................. ................................................... ...................... 58 t able 5: sts s ignal l abel m ismatch d efect c onditions .................................................. ................................................... .. 59 t able 6: t ruth t able for p ath l abel e rror c onditions .................................................. ................................................... .. 59 f igure 22. p ath o verhead i nterface t iming ................................................... ................................................... ...................... 62 f igure 23. t ransmit t ransport o verhead i nterface t iming ................................................... .............................................. 63 4.9 telecom bus interface.......................... ................................................... ............................................... 68 4.9.1 transmit telecom bus ......................... ................................................... ................................................... .......... 68 f igure 24. t ransmit t elecom b us i nterface t iming ................................................... ................................................... .......... 68 4.9.2 2khz mode in stm-1 ........................... ................................................... ................................................... ................ 69 f igure 25. c1j1v1 p ulse in stm-1 2 k h z m ode ................................................... ................................................... .................. 69 4.9.3 receive telecom bus .......................... ................................................... ................................................... ............ 69 f igure 26. r eceive t elecom b us i nterface t iming ................................................... ................................................... ............ 69 4.10 vt mapper ..................................... ................................................... ................................................... ......... 71 f igure 27. i nternal b us s tructure ................................................... ................................................... ................................... 71 f igure 28. m id b us i nterface ................................................... ................................................... .............................................. 73 f igure 29. sdh to vtm data transfer with zero pointer offset ................................................... ...................................... 73 f igure 30. vtm to sdh data transfer ................................................... ................................................... .............................. 74 f igure 31. e1 i nterface t iming (i nternal to the c hip ) .................................................. ................................................... ...... 75 f igure 32. e1 i nterface t iming (e1 synchronous mapping , i nternal to the c hip ).................................................. ............. 75 t able 7: v5 - vt p ath e rror c hecking , s ignal l abel and p ath s tatus .................................................. .............................. 76 t able 8: n2 byte structure .................................................. ................................................... ................................................. 78 t able 9: b 7- b 8 multiframe structure .................................................. ................................................... .................................. 79 t able 10: s tructure of frames # 73 - 76 of the b 7- b 8 multiframe .................................................. ..................................... 79 t able 11: k4 ( b 5- b 7) coding and interpretation .................................................. ................................................... ................. 81 t able 12: z7/k4 - vt p ath g rowth and vt p ath r emote d efect i ndication .................................................. ...................... 81 f igure 33. mkp (m ake p ayload ), one of seven mkg : m ake vt/tu g roup ................................................... ........................ 82 f igure 34. mkp (m ake p ayload ), vt/tu g roup i nterleaving ................................................... .............................................. 83 f igure 35. m ake t ributary (mkt) ............................................. ................................................... ............................................. 84 f igure 36. e xtract p ayload (xtp) ............................................. ................................................... ........................................... 85 f igure 37. r eference c locks g enerator (rcg)............................................. ................................................... .................... 86 data interface between sdh/framer and mapper ....... ................................................... .... 87 f igure 38. r eceive sdh/f ramer -atm i nterface ................................................... ................................................... ............... 87 f igure 39. t ransmit sdh/f ramer m apper i nterface ................................................... ................................................... ......... 87 f igure 40. e1 f ramer s ynchronization f low d iagram ................................................... ................................................... .... 88 f igure 41. f low of crc-4 multiframe alignment for interworking ................................................... ................................. 90 4.11 e1 phy loopback diagnostics ................... ................................................... ....................................... 93 4.11.1 e1 loopbacks................................ ................................................... ................................................... ................... 93 f igure 42. e1 f acility l oopback ................................................... ................................................... ......................................... 93 4.11.2 e1 facility i/o loopback .................... ................................................... ................................................... .......... 94 f igure 43. e1 f acility i/o l oopback ................................................... ................................................... ................................... 94 4.11.3 e1 module loopback ......................... ................................................... ................................................... .......... 95 f igure 44. e1 module l oopback ................................................... ................................................... .......................................... 95 4.11.4 alarm and auto ais .......................... ................................................... ................................................... ............. 96 f igure 45. e1 a uto ais i nsertion ................................................... ................................................... ....................................... 96 t able 13: e1 to stm-0 - response time < 125 us .................................................. ................................................... ................ 96 t able 14: stm-0 to e1 - response time < 125 usec .................................................. ................................................... ............ 96 5.0 analog front end / line interface unit (liu) se ction.............................................. ........ 98 f igure 46. s implified b lock d iagram of the liu s ection ................................................... ................................................... . 98 5.1 transmit line interface unit................... ................................................... ........................................... 99 5.1.1 jitter attenuator............................ ................................................... ................................................... ............... 99 5.1.2 taos (transmit all ones)..................... ................................................... ................................................... ......... 99
XRT86SH221 preliminary iii sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 f igure 47. taos (t ransmit a ll o nes ) .................................................. ................................................... ................................. 99 5.1.3 ataos (automatic transmit all ones).......... ................................................... .............................................. 99 f igure 48. s implified b lock d iagram of the ataos f unction ................................................... ............................................ 99 5.1.4 qrss/prbs generation......................... ................................................... ................................................... ........ 100 5.1.5 transmit pulse shaper and filter ............. ................................................... ............................................... 100 5.1.6 dmo (digital monitor output) ................. ................................................... ................................................... .. 100 5.2 line termination (ttip/tring) .................. ................................................... ........................................... 100 f igure 49. t ypical c onnection d iagram u sing i nternal t ermination ................................................... .............................. 100 5.3 receive path line interface .................... ................................................... ......................................... 101 f igure 50. s implified b lock d iagram of the r eceive p ath ................................................... ............................................... 101 5.3.1 line termination (rtip/rring)................ ................................................... ................................................... ..... 101 f igure 51. t ypical c onnection d iagram u sing i nternal t ermination ................................................... ............................. 101 5.3.2 clock and data recovery ..................... ................................................... ................................................... ... 102 f igure 52. r ecovered l ine c lock pll t iming ................................................... ................................................... .................. 102 5.3.3 recovered line clock outputs ................. ................................................... ................................................. 1 02 f igure 53. ref_rec[1:0] r ecovered l ine c lock s election to o utput p ins ................................................... .................. 102 5.3.4 rlos (receiver loss of signal)............... ................................................... ................................................... . 103 5.3.5 exlos (extended loss of signal) .............. ................................................... ................................................. 1 03 5.3.6 jitter attenuator............................ ................................................... ................................................... ............. 103 5.3.7 rxmute (receiver los with data muting) ....... ................................................... ......................................... 103 f igure 54. s implified b lock d iagram of the r x mute f unction ................................................... ....................................... 103 6.0 memory and register map........................ ................................................... .............................. 104 6.1 memory mapped i/o addressing ................... ................................................... .................................... 104 t able 15: c hannel m apping s cheme .................................................. ................................................... .................................. 104 6.2 overview of control registers.................. ................................................... ................................... 104 t able 16: m emory m ap - e1 f ramers .................................................. ................................................... ................................. 104 6.3 sdh operation control register descriptions.... ................................................... ................... 105 t able 17: i nterrupt t ype s elect (its 0 x 0001 h ) ................................................. ................................................... ............... 105 t able 18: r eceive stm c lock d etect (rstmcd 0 x 0003 h ) ................................................. ................................................ 105 t able 19: d evice id r egister (devid 0 x 0004 h ) ................................................. ................................................... ................ 106 t able 20: r evision id r egister (revid 0 x 0005 h ) ................................................. ................................................... ............. 106 t able 21: t elecom b us p arity e nable (tbpe 0 x 000b h ) ................................................. ................................................... ... 106 t able 22: t elecom b us p arity e rror e nable (tbpee 0 x 000f h ) ................................................. ........................................ 107 t able 23: o peration b lock i nterrupt r egister 1 (opir1 0 x 0012 h ) ................................................. .................................. 107 t able 24: o peration b lock i nterrupt r egister b yte 0 (opir0 0 x 0013 h ) ................................................. ......................... 108 t able 25: o peration b lock i nterrupt e nable r egister b yte 1 (opier1 0 x 0016 h ) ................................................. .......... 109 t able 26: o peration b lock i nterrupt e nable r egister b yte 0 (opier0 0 x 0017 h ) ................................................. .......... 110 t able 27: d e -s ync and au3 m apping c ontrol (dsau3mc 0 x 001b h ) ................................................. ................................. 110 t able 28: sdh l oop b ack s elect (sdhlbs 0 x 001f h ) ................................................. ................................................... ...... 111 t able 29: h igh b yte f rame b oundary l atency (hbfbl 0 x 0034 h ) ................................................. ....................................... 111 t able 30: l ow b yte f rame b oundary l atency (lbfbl 0 x 0035 h ) ................................................. ........................................ 111 t able 31: t elecom b us c ontrol 1 (tbc1 0 x 0036 h ) ................................................. ................................................... .......... 112 t able 32: t elecom b us c ontrol 0 (tbc0 0 x 0037 h ) ................................................. ................................................... .......... 113 t able 33: g eneral p urpose i nput /o utput (gpio 0 x 0047 h ) ................................................. ................................................. 11 4 t able 34: g eneral p urpose i nput /o utput d irection (gpiod 0 x 004b h ) ................................................. ............................ 114 t able 35: r ecovered l ine c lock r eference 1 (rlcr1 0 x 004d h ) ................................................. ...................................... 114 t able 36: r ecovered l ine c lock r eference 0 (rlcr0 0 x 004e h ) ................................................. ...................................... 114 t able 37: r ecovered l ine c lock s elect for rclk_rec1 and rclk_rec0 h ardware p ins .......................................... 115 t able 38: c hannel i nterrupt i ndication r egister 11 (chiir11 0 x 0054 h ) ................................................. .......................... 116 t able 39: c hannel i nterrupt i ndication r egister 10 (chiir10 0 x 0055 h ) ................................................. .......................... 116 t able 40: c hannel i nterrupt i ndication r egister 9 (chiir9 0 x 0056 h ) ................................................. .............................. 116 t able 41: c hannel i nterrupt i ndication r egister 8 (chiir8 0 x 0057 h ) ................................................. .............................. 116 t able 42: c hannel i nterrupt i ndication r egister 7 (chiir7 0 x 0058 h ) ................................................. .............................. 117 t able 43: c hannel i nterrupt i ndication r egister 6 (chiir6 0 x 0059 h ) ................................................. .............................. 117 t able 44: c hannel i nterrupt i ndication r egister 5 (chiir5 0 x 005a h ) ................................................. .............................. 117 t able 45: c hannel i nterrupt i ndication r egister 4 (chiir4 0 x 005b h ) ................................................. .............................. 117 t able 46: c hannel i nterrupt i ndication r egister 3 (chiir3 0 x 005c h ) ................................................. .............................. 118 t able 47: c hannel i nterrupt i ndication r egister 2 (chiir2 0 x 005d h ) ................................................. .............................. 118 t able 48: c hannel i nterrupt i ndication r egister 1 (chiir1 0 x 005e h ) ................................................. .............................. 118 t able 49: c hannel i nterrupt i ndication r egister 0 (chiir0 0 x 005f h ) ................................................. .............................. 118 6.4 receive transport overhead operation control re gister descriptions..................... 119 t able 50: r eceive stm-0/stm-1 t ransport c ontrol r egister 1 (rtcr1 = 0 x 0202) ............................................. ........... 119 t able 51: r eceive stm-0/stm-1 t ransport c ontrol r egister 0 (rtcr0 = 0 x 0203) ............................................. .......... 119 t able 52: r eceive stm-0/stm-1 t ransport s tatus r egister 1 (rtsr1 = 0 x 0206) ............................................. .............. 121 t able 53: r eceive stm-0/stm-1 t ransport s tatus r egister 0 (rtsr0 = 0 x 0207) ............................................. ............. 122 t able 54: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 2 (rtisr2 = 0 x 0209) ........................................ 124
preliminary XRT86SH221 iv rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu t able 55: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 1 (rtisr1 = 0 x 020a) ........................................ 125 t able 56: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 0 (rtisr0 = 0 x 020b) ........................................ 127 t able 57: r eceive stm-0/stm-1 t ransport i nterrupt e nable r egister 2 (rtier2 = 0 x 020d) ........................................ 129 t able 58: r eceive stm-0/stm-1 t ransport i nterrupt e nable r egister 1 (rtier1 = 0 x 020e) ........................................ 130 t able 59: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 0 (rtier0 = 0 x 020f) ........................................ 132 t able 60: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 3 (b1becr3 = 0 x 0210) ........................... 133 t able 61: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 2 (b1becr2 = 0 x 0211) ........................... 134 t able 62: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 1 (b1becr1 = 0 x 0212) ........................... 134 t able 63: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 0 (b1becr0 = 0 x 0213) ........................... 135 t able 64: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 3 (b2becr3= 0 x 0214) ............................ 135 t able 65: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 2 (b2becr2 = 0 x 0215) ........................... 136 t able 66: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 1 (b2becr1 = 0 x 0216) ........................... 136 t able 67: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 0 (b2becr0 = 0 x 0217) ........................... 137 t able 68: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 3 (reilecr3 = 0 x 0218) ............................... 137 t able 69: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 2 (reilecr2 = 0 x 0219) ............................... 138 t able 70: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 1 (reilecr1 = 0 x 021a) .............................. 138 t able 71: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 0 (reilecr0 = 0 x 021b) .............................. 139 t able 72: r eceive stm-0/stm-1 t ransport - r eceived k1 b yte v alue r egister (rk1bvr = 0 x 021f) ............................ 139 t able 73: r eceive stm-0/stm-1 t ransport - r eceived k2 b yte v alue r egister (rk2bvr = 0 x 0223) ............................. 139 t able 74: r eceive stm-0/stm-1 t ransport - r eceived s1 b yte v alue r egister (rs1bvr = 0 x 0227) ............................. 140 t able 75: r eceive stm-0/stm-1 t ransport - r eceive i n -s ync t hreshold r egister (ristr = 0 x 022b) .......................... 140 t able 76: r eceive stm-0/stm-1 t ransport - los t hreshold v alue 1 (lostv1 = 0 x 022e) ............................................. 140 t able 77: r eceive stm-0/stm-1 t ransport - los t hreshold v alue 0 (lostv0 = 0 x 022f) ............................................. 141 t able 78: r eceive stm-0/stm-1 t ransport - r eceive sf set m onitor i nterval 2 (rsfsmi2= 0 x 0231) ......................... 141 t able 79: r eceive stm-0/stm-1 t ransport - r eceive sf set m onitor i nterval 1 (rsfsmi1 = 0 x 0232) ........................ 141 t able 80: r eceive stm-0/stm-1 t ransport - r eceive sf set m onitor i nterval 0 (rsfsmi0 = 0 x 0233) ........................ 143 t able 81: r eceive stm-0/stm-1 t ransport - r eceive sf set t hreshold 1 (rsfst1= 0 x 0236) ...................................... 143 t able 82: r eceive stm-0/stm-1 t ransport - r eceive sf set t hreshold 0 (rsfst0 = 0 x 0237) ..................................... 144 t able 83: r eceive stm-0 t ransport - r eceive sf clear t hreshold 2 (rsfct2= 0 x 023a) ............................................ 1 44 t able 84: r eceive stm-0 t ransport - r eceive sf clear t hreshold 1 (rsfct1 = 0 x 023b) ........................................... 14 4 t able 85: r eceive stm-0 t ransport - r eceive sd s et m onitor i nterval 0 (rsfct0 = 0 x 023d) ..................................... 145 t able 86: r eceive stm-0 t ransport - r eceive sd s et m onitor i nterval 1 (rsdsmi1 = 0 x 023e) ................................... 145 t able 87: r eceive stm-0 t ransport - r eceive sd s et m onitor i nterval 0 (rsdsmi0 = 0 x 023f) .................................... 146 t able 88: r eceive stm-0 t ransport - r eceive sd set t hreshold 1 (rsdst1= 0 x 0242) ............................................. .... 146 t able 89: r eceive stm-0 t ransport - r eceive sd set t hreshold 0 (rsdst0 = 0 x 0243) ............................................. ... 147 t able 90: r eceive stm-0 t ransport - r eceive sd clear t hreshold 1 (rsdct1= 0 x 0246) ............................................ 1 47 t able 91: r eceive stm-0 t ransport - r eceive sd clear t hreshold 0 (rsdct0 = 0 x 0247) ........................................... 14 7 t able 92: r eceive stm-0 t ransport - f orce sef d efect c ondition r egister (fsdcr = 0 x 024b) ................................. 148 t able 93: r eceive stm-0 t ransport - r eceive s ection t race m essage b uffer c ontrol r egister (rstmbcr = 0 x 024f) 149 t able 94: r eceive stm-0 t ransport - r eceive sd b urst e rror t olerance 1 (rsdbet1 = 0 x 0252) ............................... 150 t able 95: r eceive stm-0 t ransport - r eceive sd b urst e rror t olerance 0 (rsdbet0 = 0 x 0253) ............................... 150 t able 96: r eceive stm-0 t ransport - r eceive sf b urst e rror t olerance 1 (rsfbet1 = 0 x 0256) ............................... 151 t able 97: r eceive stm-0 t ransport - r eceive sf b urst e rror t olerance 0 (rsfbet0 = 0 x 0257) ............................... 151 t able 98: r eceive stm-0 t ransport - r eceive sd c lear m onitor i nterval 2 (rsdcmi2= 0 x 0259) ................................. 152 t able 99: r eceive stm-0 t ransport - r eceive sd c lear m onitor i nterval 1 (rsdcmi1 = 0 x 025a) ............................... 152 t able 100: r eceive stm-0 t ransport - r eceive sd c lear m onitor i nterval 0 (rsdcmi0 = 0 x 025b) ............................. 153 t able 101: r eceive stm-0 t ransport - r eceive sf c lear m onitor i nterval 2 (rsfcmi2= 0 x 025d) ............................... 153 t able 102: r eceive stm-0 t ransport - r eceive sf c lear m onitor i nterval 1 (rsfcmi1 = 0 x 025e) .............................. 154 t able 103: r eceive stm-0 t ransport - r eceive sf c lear m onitor i nterval 0 (rsfcmi0 = 0 x 025f) .............................. 154 t able 104: r eceive stm-0 t ransport - a uto ais c ontrol r egister (aaiscr = 0 x 0263) ............................................. .... 155 t able 105: r eceive stm-0/stm-1 t ransport - a1, a2 b yte e rror c ount r egister 1 (a1a2be1 = 0 x 026e) ................... 158 t able 106: r eceive stm-0/stm-1 t ransport - a1, a2 b yte e rror c ount r egister 0 (a1a2be0 = 0 x 026f) ................... 158 6.5 receive path overhead operation control registe r descriptions ................................. 159 t able 107: r eceive stm-0 p ath - r eceive c ontrol r egister 0 (rcr0 = 0 x 0283) ............................................. ................. 159 t able 108: r eceive stm-0 p ath - c ontrol r egister (pcr = 0 x 0286) ............................................. .................................... 160 t able 109: r eceive stm-0 p ath - sdh r eceive poh s tatus (rpohs = 0 x 0287) ............................................. .................. 160 t able 110: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt s tatus 2 (rpis2 = 0 x 0289) ............................................. 162 t able 111: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt s tatus 1 (rpis1 = 0 x 028a) ............................................ 1 63 t able 112: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt s tatus 0 (rpis0 = 0 x 028b) ............................................ 1 65 t able 113: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt e nable 2 (rpie2 = 0 x 028d) ............................................ 1 68 t able 114: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt e nable 1 (rpie1 = 0 x 028e) ............................................ 1 69 t able 115: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt e nable 0 (rpie0 = 0 x 028f) ............................................. 171 t able 116: r eceive stm-0 p ath - sdh r eceive rdi-p r egister (rrdipr = 0 x 0293) ............................................. ............ 173 t able 117: r eceive stm-0 p ath - r eceived p ath l abel v alue (rplv = 0 x 0296) ............................................. ................... 173 t able 118: r eceive stm-0 p ath - e xpected p ath l abel v alue (eplv = 0 x 0297) ............................................. ................... 174
XRT86SH221 preliminary v sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 t able 119: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 3 (b3becr3 = 0 x 0298) ............................................. . 174 t able 120: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 2 (b3becr2 = 0 x 0299) ............................................. . 175 t able 121: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 1 (b3becr1 = 0 x 029a) ............................................. . 175 t able 122: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 0 (b3becr0 = 0 x 029b) ............................................. . 176 t able 123: r eceive stm-0 p ath - rei-p e vent c ount r egister 3 (reipecr3 = 0 x 029c) ............................................. .... 176 t able 124: r eceive stm-0 p ath - rei-p e vent c ount r egister 2 (reipecr2 = 0 x 029d) ............................................. .... 177 t able 125: r eceive stm-0 p ath - rei-p e vent c ount r egister 1 (reipecr1 = 0 x 029e) ............................................. ..... 177 t able 126: r eceive stm-0 p ath - rei-p e vent c ount r egister 0 (reipecr0 = 0 x 029f) ............................................. ..... 178 t able 127: r eceive stm-0 p ath - r eceive p ath t race m essage b uffer c ontrol r egister (rptmbcr = 0 x 02a3) ....... 178 t able 128: r eceive stm-0 p ath - p ointer v alue 1 (pv1 = 0 x 02a6) ............................................. ........................................ 179 t able 129: r eceive stm-0 p ath - p ointer v alue 0 (pv0 = 0 x 02a7) ............................................. ........................................ 180 t able 130: r eceive stm-0 p ath - r eceive a uto ais - c2 b yte v alue r egister (aisc2vr = 0 x 02b9) .............................. 180 t able 131: r eceive stm-0 p ath - r eceive a uto ais - c2 b yte c ontrol r egister (aisc2cr = 0 x 02ba) ......................... 180 t able 132: r eceive stm-0 p ath - auto ais c ontrol r egister (autoacr = 0 x 02bb) ............................................. ........ 181 t able 133: r eceive stm-0 p ath - sdh r eceive a uto a larm r egister (raar = 0 x 02c3) ............................................. ..... 183 t able 134: r eceive stm-0 p ath - r eceive n egative p ointer a djustment c ount r egister 1 (rnpacr1 = 0 x 02c4) ....... 184 t able 135: r eceive stm-0 p ath - r eceive n egative p ointer a djustment c ount r egister 0 (rnpacr0 = 0 x 02c5) ....... 184 t able 136: r eceive stm-0 p ath - r eceive p ositive p ointer a djustment c ount r egister 1 (rppacr1 = 0 x 02c6) ........ 185 t able 137: r eceive stm-0 p ath - r eceive p ositive p ointer a djustment c ount r egister 0 (rppacr0 = 0 x 02c7) ........ 185 t able 138: r eceive stm-0 p ath - r eceive j1 b yte c apture r egister (rj1bcr = 0 x 02d3) ............................................. .. 185 t able 139: r eceive stm-0 p ath - r eceive b3 b yte c apture r egister (rb3bcr = 0 x 02d7) ............................................. 186 t able 140: r eceive stm-0 p ath - r eceive c2 b yte c apture r egister (rc2bcr = 0 x 02db) ............................................. 186 t able 141: r eceive stm-0 p ath - r eceive g1 b yte c apture r egister (rg1bcr = 0 x 02df) ............................................ 1 86 t able 142: r eceive stm-0 p ath - r eceive f2 b yte c apture r egister (rf2bcr = 0 x 02e3) ............................................. . 186 t able 143: r eceive stm-0 p ath - r eceive h4 b yte c apture r egister (rh4bcr = 0 x 02e7) ............................................. 187 t able 144: r eceive stm-0 p ath - r eceive z3 b yte c apture r egister (rz3bcr = 0 x 02eb) ............................................. . 187 t able 145: r eceive stm-0 p ath - r eceive z4 (k3) b yte c apture r egister (rz4bcr = 0 x 02ef) ...................................... 187 t able 146: r eceive stm-0 p ath - r eceive z5 b yte c apture r egister (rz5bcr = 0 x 02f3) ............................................. . 187 6.6 transmit transport overhead port control regist er descriptions ............................. 188 t able 147: t ransmit stm-0 s ection c ontrol r egister 3 (tscr3 0 x 0700 h ) ................................................. ..................... 188 t able 148: t ransmit stm-0 s ection c ontrol r egister 2 (tscr2 0 x 0701 h ) ................................................. ..................... 188 t able 149: t ransmit stm-0 s ection c ontrol r egister 1 (tscr1 0 x 0702 h ) ................................................. ..................... 189 t able 150: s ource of m0/m1 b yte .................................................. ................................................... ..................................... 190 t able 151: t ransmit stm-0 s ection c ontrol r egister 0 (tscr0 0 x 0703 h ) ................................................. ..................... 191 t able 152: t ransmit stm-0 s ection a1 b yte e rror m ask (tsa1em 0 x 0717 h ) ................................................. ................. 193 t able 153: t ransmit stm-0 s ection a2 b yte e rror m ask (tsa2em 0 x 071f h ) ................................................. ................. 193 t able 154: t ransmit stm-0 s ection b1 b yte e rror m ask (tsb1em 0 x 0723 h ) ................................................. ................. 194 t able 155: t ransmit stm-0 s ection b2 b yte s elect e rror e nable (tsb2see 0 x 0727 h ) ................................................. 194 t able 156: t ransmit stm-0 s ection b2 b yte e rror m ask (tsb2em 0 x 072b h ) ................................................. ................. 195 t able 157: t ransmit stm-0 s ection k2 b yte v alue r egister (tsk2vr 0 x 072e h ) ................................................. ............ 196 t able 158: t ransmit stm-0 s ection k1 b yte v alue r egister (tsk1vr 0 x 072f h ) ................................................. ............ 196 t able 159: t ransmit stm-0 s ection ms-rdi c ontrol r egister (tsmsrdicr 0 x 0733 h ) ................................................. . 197 t able 160: t ransmit stm-0 s ection m0m1 b yte v alue r egister (tsm0m1vr 0 x 0737 h ) ................................................. . 198 t able 161: t ransmit stm-0 s ection - s1 b yte v alue r egister (tss1vr 0 x 073b) ............................................. ................ 198 t able 162: t ransmit stm-0 s ection - f1 b yte v alue r egister (tsf1vr 0 x 073f) ............................................. ............... 198 t able 163: t ransmit stm-0 s ection - e1 b yte v alue r egister (tse1vr 0 x 0743) ............................................. ............... 199 t able 164: t ransmit stm-0 s ection - e2 b yte v alue r egister (tse2vr 0 x 0747) ............................................. ............... 199 t able 165: t ransmit stm-0 s ection - j0 b yte v alue r egister (tsj0vr 0 x 074b) ............................................. ................. 199 t able 166: t ransmit stm-0 s ection - t ransmitter j0 b yte c ontrol r egister (tsj0cr 0 x 074f) ................................... 200 6.7 transmit path overhead processor block register s .................................................. ......... 201 t able 167: t ransmit stm-0 p ath c ontrol r egister - b yte 2 (tpcr2 0 x 0781) ............................................. ..................... 201 t able 168: t ransmit stm-0 p ath c ontrol r egister - b yte 1 (tpcr1 0 x 0782) ............................................. ..................... 202 t able 169: t ransmit stm-0 p ath c ontrol r egister - b yte 0 (tpcr0 0 x 0783) ............................................. ..................... 203 t able 170: t ransmit stm-0 p ath j1 b yte v alue r egister (tpj1vr 0 x 0793) ............................................. ......................... 205 t able 171: t ransmit stm-0 p ath b3 b yte e rror m ask r egister (tpb3em 0 x 0797) ............................................. ............ 205 t able 172: t ransmit stm-0 p ath c2 b yte v alue r egister (tpc2vr 0 x 079b) ............................................. ....................... 205 t able 173: t ransmit stm-0 p ath g1 b yte v alue r egister (tpg1vr 0 x 079f) ............................................. ...................... 206 t able 174: t ransmit stm-0 p ath f2 b yte v alue r egister (tpf2vr 0 x 07a3) ............................................. ....................... 206 t able 175: t ransmit stm-0 p ath h4 b yte v alue r egister (tph4vr 0 x 07a7) ............................................. ....................... 206 t able 176: t ransmit stm-0 p ath z3 b yte v alue r egister (tpz3vr 0 x 07ab) ............................................. ....................... 207 t able 177: t ransmit stm-0 p ath z4 b yte v alue r egister (tpz4vr 0 x n9af) ............................................. ....................... 207 t able 178: t ransmit stm-0 p ath z5 b yte v alue r egister (tpz5vr 0 x 07b3) ............................................. ....................... 207 t able 179: t ransmit stm-0 p ath p ointer c ontrol r egister (tppcr 0 x 07b7) ............................................. .................... 208 t able 180: t ransmit stm-0 p ath j1 c ontrol r egister (tpj1cr 0 x 07bb) ............................................. ............................ 210 t able 181: t ransmit stm-0 p ath a rbitrary h1 p ointer r egister (tph1pr 0 x 07bf) ............................................. .......... 210 t able 182: t ransmit stm-0 p ath a rbitrary h2 p ointer r egister (tph2pr 0 x 07c3) ............................................. .......... 211
preliminary XRT86SH221 vi rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu t able 183: t ransmit stm-0 p ath c urrent p ointer b yte r egister - b yte 1 (tpcpr1 0 x 07c6) ........................................ 211 t able 184: t ransmit stm-0 p ath c urrent p ointer b yte r egister - b yte 0 (tpcpr0 0 x 07c7) ........................................ 211 t able 185: t ransmit stm-0 p ath hp-rdi c ontrol r egister - b yte 2 (tphp-rdicr2 0 x 07c9) ........................................ 212 t able 186: t ransmit stm-0 p ath hp-rdi c ontrol r egister - b yte 1 (tphp-rdicr1 0 x 07ca) ....................................... 213 t able 187: t ransmit stm-0 p ath hp-rdi c ontrol r egister - b yte 0 (tphp-rdicr0 0 x 07cb) ....................................... 214 t able 188: t ransmit stm-0 p ath s erial p ort c ontrol r egister (tpspcr 0 x 07cf) ............................................. .......... 214 6.8 global e1 line interface unit register descript ions (liu) ......................................... ........... 215 t able 189: g lobal l ine i nterface c ontrol r egister 5 (glicr5 0 x 0100 h ) ................................................. ....................... 215 t able 190: g lobal l ine i nterface c ontrol r egister 4 (glicr4 0 x 0101 h ) ................................................. ........................ 216 t able 191: g lobal l ine i nterface c ontrol r egister 3 (glicr3 0 x 0102 h ) ................................................. ........................ 216 t able 192: g lobal l ine i nterface c ontrol r egister 2 (glicr2 0 x 0103 h ) ................................................. ........................ 217 t able 193: g lobal l ine i nterface c ontrol r egister 1 (glicr1 0 x 0104 h ) ................................................. ........................ 217 t able 194: g lobal l ine i nterface c ontrol r egister 0 (glicr0 0 x 0105 h ) ................................................. ........................ 217 6.9 individual channel e1 line interface unit regis ter descriptions (liu) ............................ 218 t able 195: c hannel l ine i nterface c ontrol r egister 9 (clicr9 0 x n000 h ) ................................................. ..................... 218 t able 196: c hannel l ine i nterface c ontrol r egister 8 (clicr8 0 x n001 h ) ................................................. ..................... 219 t able 197: c hannel l ine i nterface c ontrol r egister 7 (clicr7 0 x n002 h ) ................................................. ..................... 220 t able 198: c hannel l ine i nterface c ontrol r egister 6 (clicr6 0 x n003 h ) ................................................. ..................... 221 t able 199: c hannel l ine i nterface c ontrol r egister 5 (clicr5 0 x n004 h ) ................................................. ..................... 222 t able 200: c hannel l ine i nterface c ontrol r egister 4 (clicr4 0 x n005 h ) ................................................. ..................... 223 t able 201: c hannel l ine i nterface c ontrol r egister 3 (clicr3 0 x n006 h ) ................................................. ..................... 224 t able 202: c hannel l ine i nterface c ontrol r egister 2 (clicr2 0 x n007 h ) ................................................. ..................... 225 t able 203: c hannel l ine i nterface c ontrol r egister 1 (clicr1 0 x n010 h ) ................................................. ..................... 226 t able 204: c hannel l ine i nterface c ontrol r egister 0 (clicr0 0 x n011 h ) ................................................. ..................... 226 6.10 e1 synchronization framer register description s (egress direction only) ............. 228 t able 205: c lock s elect r egister (csr 0 x n100 h ) ................................................. ................................................... .......... 228 t able 206: s lip b uffer c ontrol r egister (sbcr 0 x n116 h ) ................................................. ............................................... 229 t able 207: fifo l atency r egister (fifolr 0 x n117 h ) ................................................. ................................................... ..... 229 t able 208: f raming s elect r egister r e -s ync (fsrrs 0 x n10b h ) ................................................. ...................................... 230 t able 209: b lock i nterrupt s tatus r egister (bisr 0 x nb00 h ) ................................................. .......................................... 231 t able 210: b lock i nterrupt e nable r egister (bier 0 x nb01 h ) ................................................. .......................................... 231 t able 211: a larm and e rror s tatus r egister (aesr 0 x nb02 h ) ................................................. ........................................ 232 t able 212: a larm and e rror i nterrupt e nable r egister (aeier 0 x nb03 h ) ................................................. ..................... 232 t able 213: f ramer i nterrupt s tatus r egister (fisr 0 x nb04 h ) ................................................. ........................................ 233 t able 214: f ramer i nterrupt e nable r egister (fier 0 x nb05 h ) ................................................. ........................................ 234 t able 215: s lip b uffer s tatus r egister (sbsr 0 x nb08 h ) ................................................. ................................................. 23 5 t able 216: s lip b uffer i nterrupt e nable r egister (sbier 0 x nb09 h ) ................................................. ............................... 235 6.11 vt mapping operation control register descript ions............................................... .......... 236 t able 217: g lobal vt-m apper b lock - vt m apper b lock c ontrol r egister (vtmcr = 0 x 0c03) .................................... 236 t able 218: g lobal vt m apper b lock - t est p attern c ontrol r egister 1 (vtmtpcr1 = 0 x 0c0e) ................................. 237 t able 219: g lobal vt-m apper b lock - t est p attern c ontrol r egister 0 (vtmtpcr0 = 0 x 0c0f) ................................. 238 t able 220: g lobal vt-d e m apper b lock - t est p attern d rop r egister 1 (vtdtpdr1 = 0 x 0c12) ................................... 239 t able 221: g lobal vt-d e m apper b lock - t est p attern d rop r egister 0 (vtdtpdr0 = 0 x 0c13) ................................... 241 t able 222: g lobal vt-d e m apper - t est p attern d etector e rror c ount r egister 1 (vtdtpdecr1 = 0 x 0c16) .......... 243 t able 223: g lobal vt-d e m apper - t est p attern d etector e rror c ount r egister 0 (vtdtpdecr0 = 0 x 0c17) .......... 243 t able 224: g lobal vt-m apper - t ransmit t ributary s ize s elect r egister 1 (vtmttssr1 = 0 x 0c1a) ........................... 244 t able 225: g lobal vt-m apper - t ransmit t ributary s ize s elect r egister 0 (vtmttssr0 = 0 x 0c1b) ........................... 246 t able 226: g lobal vt-d e m apper - r eceive t ributary s ize s elect r egister 1 (vtdrtssr1 = 0 x 0c1e) ........................ 248 t able 227: g lobal vt-d e m apper - r eceive t ributary s ize s elect r egister 0 (vtdrtssr0 = 0 x 0c1f) ......................... 249 t able 228: c hannel c ontrol - vt-m apper e1 i nsertion c ontrol r egister 1 (vtme1icr1 = 0 x nd42) ........................... 251 t able 229: c hannel c ontrol - vt-m apper e1 i nsertion c ontrol r egister 0 (vtme1icr0 = 0 x nd43) ........................... 253 t able 230: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 3 (vtde1dcr3 = 0 x nd44) ............................ 255 t able 231: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 2 (vtde1dcr2 = 0 x nd45) ............................ 255 t able 232: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 1 (vtde1dcr1 = 0 x nd46) ............................ 256 t able 233: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 0 (vtde1dcr0 = 0 x nd47) ............................ 257 t able 234: c hannel c ontrol - vt-d e m apper bip-2 e rror c ount r egister 1 (vtdbip2ecr1 = 0 x nd4a) ...................... 260 t able 235: c hannel c ontrol - vt-d e m apper bip-2 e rror c ount r egister 0 (vtdbip2ecr0 = 0 x nd4b) ...................... 260 t able 236: c hannel c ontrol - vt-d e m apper rei-v e vent c ount r egister 1 (vtdreiecr1 = 0 x nd4e) ........................ 261 t able 237: c hannel c ontrol - vt-d e m apper rei-v e vent c ount r egister 0 (vtdreiecr0 = 0 x nd4f) ........................ 261 t able 238: c hannel c ontrol - vt-d e m apper r eceive aps r egister 1 (vtdrapsr1 = 0 x nd52) .................................... 262 t able 239: c hannel c ontrol - vt-d e m apper r eceive aps r egister 0 (vtdrapsr0 = 0 x nd53) .................................... 264 t able 240: c hannel c ontrol - vt-m apper t ransmit aps r egister 1 (vtmtapsr1 = 0 x nd56) ....................................... 266 t able 241: c hannel c ontrol - vt-m apper t ransmit aps/k4 r egister 0 (vtmtapsr0 = 0 x nd57) ................................. 267 t able 242: c hannel c ontrol - vt-d e m apper t andem c onnection - r eceive bip-2 e rror c ount r egister 2 (vtdtcbip2ecr = 0 x nd59) ............................................. ................................................... ................................................... .............. 267 t able 243: c hannel c ontrol - vt-d e m apper t andem c onnection - r eceive rei-v e vent c ount r egister 1 (vtdtcreiecr
XRT86SH221 preliminary vii sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 = 0 x nd5b) ............................................. ................................................... ................................................... .............. 267 t able 244: c hannel c ontrol - vt-d e m apper t andem c onnection - r eceive oei e vent c ount r egister 0 (vtdtcoeiecr = 0 x nd5f) ............................................. ................................................... ................................................... ................. 268 t able 245: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 1 (vtdcsr1 = 0 x nd60) ................................ 268 t able 246: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 0 (vtdcsr0 = 0 x nd61) ................................ 269 t able 247: c hannel c ontrol - vt-d e m apper t andem c onnection s tatus r egister (vtdtcsr = 0 x nd62) 271 t able 248: c hannel c ontrol - vt-d e m apper j2 b yte s tatus r egister (vtdj2bsr = 0 x nd63) ...................................... 273 t able 249: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 1 (vtdcsr1 = 0 x nd64) ................................ 274 t able 250: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 0 (vtdcsr0 = 0 x nd65) ................................ 275 t able 251: c hannel c ontrol - vt-d e m apper t andem c onnection i nterrupt s tatus r egister (vtdtcisr = 0 x nd66) 277 t able 252: c hannel c ontrol - vt-d e m apper i nterrupt s tatus r egister 0 (vtdisr0 = 0 x nd67) ................................... 279 t able 253: c hannel c ontrol - vt-d e m apper i nterrupt e nable r egister 2 (vtdier2 = 0 x nd68) ................................... 280 t able 254: c hannel c ontrol - vt-d e -m apper i nterrupt e nable r egister 1 (vtdier1 = 0 x nd69) ................................. 281 t able 255: c hannel c ontrol - vt-d e -m apper t andem c onnection i nterrupt e nable r egister (vtdtcier = 0 x nd6a) 283 t able 256: c hannel c ontrol - vt-d e -m apper i nterrupt e nable r egister 0 (vtdier0 = 0 x nd6b) ................................. 285 t able 257: c hannel c ontrol - vt-d e -m apper p ath t race b uffer c ontrol r egister (vtdptbcr = 0 x nd71) .............. 286 t able 258: c hannel c ontrol - vt-d e -m apper a uto ais c ontrol r egister 1 (vtdaaiscr1 = 0 x nd72) ......................... 288 t able 259: c hannel c ontrol - vt-d e -m apper a uto ais c ontrol r egister 0 (vtdaaiscr0 = 0 x nd73) ......................... 290 t able 260: c hannel c ontrol - vt-m apper t ransmit j2 b yte v alue r egister (vtmj2vr = 0 x nd76) ............................... 293 t able 261: c hannel c ontrol - vt-m apper t ransmit n2 b yte v alue r egister (vtmn2vr = 0 x nd77) ............................. 293 t able 262: c hannel c ontrol - vt-m apper t ransmit p ath t race m essage c ontrol r egister (vtmptmcr = 0 x nd79) 294 t able 263: c hannel c ontrol - vt-m apper t ransmit n2 c ontrol r egister (vtmn2cr = 0 x nd7b) ................................. 296 t able 264: c hannel c ontrol - vt-m apper t ransmit t andem c onnection rdi-v c ontrol r egister 1 (vtmtcrdicr1 = 0 x nd7e) ............................................. ................................................... ................................................... ................. 297 t able 265: c hannel c ontrol - vt-m apper t ransmit t andem c onnection rdi-v c ontrol r egister 0 (vtmtcrdicr0 = 0 x nd7f) ............................................. ................................................... ................................................... ................. 298 t able 266: c hannel c ontrol - vt-m apper t ransmit t andem c onnection odi-v c ontrol r egister 1 (vtmtcodicr1 = 0 x nd82) ............................................. ................................................... ................................................... ................. 300 t able 267: c hannel c ontrol - vt-m apper t ransmit t andem c onnection odi-v c ontrol r egister 0 (vtmtcodicr0 = 0 x nd83) ............................................. ................................................... ................................................... ................. 301 t able 268: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 3 (vtmrdicr3 = 0 x nd84) ..................... 303 t able 269: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 2 (vtmrdicr2 = 0 x nd85) ..................... 304 t able 270: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 1 (vtmrdicr1 = 0 x nd86) ..................... 305 t able 271: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 0 (vtmrdicr0 = 0 x nd87) ..................... 306 t able 272: r eceive j2 t race i dentifier m essage m emory b uffer (vtd j2mem00 = 0 x ne00 - vtdj2mem3f = 0 x ne3f) ............................................. ................................................... ......................................... 307 t able 273: r eceive n2 a ccess p oint i dentifier m essage m emory b uffer (vtd n2mem20 = 0 x ne20 - vtdn2mem2f = 0 x ne2f) ............................................. ................................................... ...................................... 307 t able 274: t ransmit j2 t race i dentifier m essage m emory b uffer (vtm j2mem00 = 0 x nf00 - vtmj2mem3f = 0 x nf3f) ............................................. ................................................... ........................................ 308 t able 275: t ransmit n2 a cess p oint i dentifier m essage m emory b uffer (vtm n2mem20 = 0 x nf20 - vtmn2mem2f = 0 x nf2f) ............................................. ................................................... ..................................... 308 7.0 microprocessor interface timing ................ ................................................... ..................... 309 7.1 microprocessor interface timing - intel asynchr onous mode ......................................... . 309 f igure 55. i ntel -a synchronous m ode t iming - w rite o peration ................................................... ...................................... 309 t able 276 i ntel a synchronous m ode t iming - w rite o peration .................................................. ....................................... 310 f igure 56. i ntel -a synchronous m ode t iming - r ead o peration ................................................... ....................................... 310 t able 277 i ntel a synchronous m ode t iming - r ead o peration .................................................. ......................................... 310 7.2 microprocessor interface timing - motorola asyn chronous (68k) mode...................... 311 f igure 57. m otorola -a synchronous m ode t iming - w rite o peration ................................................... ............................. 311 t able 278 m otorola (68k) a synchronous m ode t iming i nformation - w rite o peration .................................................. 311 7.2.1 motorola-asynchronous mode timing - read ope ration............................................. ..................... 312 f igure 58. m otorola -a synchronous m ode t iming - r ead o peration ................................................... .............................. 312 t able 279 m otorola (68k) a synchronous m ode t iming - r ead o peration .................................................. ...................... 312 7.3 powerpc 403 synchronous mode:.................. ................................................... ................................. 313 f igure 59. p ower pc 403 m ode t iming - w rite o peration ................................................... ................................................. 3 13 t able 280 p ower pc403 m ode t iming - w rite o peration .................................................. ................................................... 313 f igure 60. p ower pc 403 m ode t iming - r ead o peration ................................................... .................................................. 314 t able 281 p ower pc403 m ode t iming - r ead o peration .................................................. ................................................... . 314 7.4 microprocessor interface timing - mcp860 synchr onous mode ......................................... 315 f igure 61. mpc86x m ode t iming - w rite o peration ................................................... ................................................... ....... 315 t able 282 mpc86x m ode t iming - w rite o peration .................................................. ................................................... ......... 315 t able 283 mpc86x t iming i nformation - r ead o peration .................................................. .................................................. 3 16 f igure 62. mpc86x m ode t iming - r ead o peration ................................................... ................................................... ........ 316 8.0 interface timing specifications................ ................................................... .......................... 317
preliminary XRT86SH221 viii rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.1 stm-0/stm-1 telecom bus interface timing inform ation .............................................. ............ 317 8.2 the transmit stm-0/stm-1 telecom bus interface timing - stm-0 applications ............... 317 f igure 63. a n i llustration of the w aveforms of the s ignals that are output via the t ransmit stm-0/stm-1 t elecom b us i nterface ( for stm-0 a pplications ) .................................................. ................................................... ................. 317 t able 284 t iming i nformation for the t ransmit stm-0 t elecom b us i nterface - stm-0 a pplications ........................... 318 8.3 the transmit stm-0/stm-1 telecom bus interface timing - stm-1 slot master applications 318 f igure 64. a n i llustration of the w aveforms of the s ignals that are output via the t ransmit stm-0/stm-1 t elecom b us i nterface ( for stm-1 a pplications ) .................................................. ................................................... ................. 318 f igure 65. a n i llustration of the timing relationships between the t x sbfp_in_out output pin , and the t x a_clk output pin , within the t ransmit stm-1 t elecom b us i nterface (s lot m aster m ode a pplication ) ............................... 319 t able 285 t iming i nformation for the t ransmit stm-0/stm-1 t elecom b us i nterface - stm-1 s lot m aster a pplications 319 8.4 the transmit stm-0/stm-1 telecom bus interface timing - stm-1 slot slave applications 320 f igure 66. a n i llustration of the w aveforms of the s ignals that are output via the t ransmit stm-0/stm-1 t elecom b us i nterface ( for stm-1 a pplications ) .................................................. ................................................... ................. 320 f igure 67. a n i llustration of the timing relationships between the t x sbfp input pin and the t x a_clk output pin within the t ransmit stm-0/stm-1 t elecom b us i nterface (stm-1 s lot s lave a pplications ) ........................................... 320 t able 286 t iming i nformation for the t ransmit stm-0/stm-1 t elecom b us i nterface - stm-1 s lot s lave a pplications 321 8.5 the receive stm-0/stm-1 telecom bus interface t iming - stm-0 applications.................. 321 f igure 68. a n i llustration of the w aveforms of the s ignals that are i nput via the r eceive stm-0/stm-1 t elecom b us i n - terface ................................................... ................................................... ................................................... ............ 321 t able 287 t iming i nformation for the r eceive stm-0/stm-1 t elecom b us i nterface - stm-0 a pplications ................. 321 8.6 the receive stm-0/stm-1 telecom bus interface t iming - stm-1 applications.................. 322 f igure 69. a n i llustration of the w aveforms of the s ignals that are i nput via the r eceive stm-0/stm-1 t elecom b us i n - terface ................................................... ................................................... ................................................... ............ 322 t able 288 t iming i nformation for the r eceive stm-0/stm-1 t elecom b us i nterface - stm-1 a pplications ................. 322 8.7 stm-0 liu interface timing information ......... ................................................... .............................. 323 8.7.1 receive stm-0/stm-1 liu interface timing..... ................................................... ............................................ 323 f igure 70. a n i llustration of the w aveforms of the r eceive stm-0/stm-1 signals that are input to the r eceive stm-0/ stm-1 liu i nterface b lock - s hared p ort ................................................... ................................................... ..... 323 t able 289 t iming i nformation for the r eceive stm-0/stm-1 liu i nterface when the r eceive stm-0/stm-1 toh p rocessor block has been configured to sample the r x stm0data signal upon the rising edge of the r x stm0clk signal 323 8.7.2 transmit stm-0/stm-1 liu interface timing.... ................................................... .......................................... 324 f igure 71. a n i llustration of the w aveforms of the stm-0/stm-1 signals that are output from the t ransmit stm-0/stm- 1 liu i nterface - d edicated p ort ................................................... ................................................... ..................... 324 t able 290 t iming i nformation for the t ransmit stm-0/stm-1 liu i nterface when the t ransmit stm-0/stm-1 toh p roces - sor block has been configured to update the t x stm0data signal upon the rising edge of the t x stm0clk signal 324 8.8 transmit stm-0/stm-1 toh and poh data input por t .................................................. ................. 325 f igure 72. i llustration of t iming w ave - form of the t ransmit stm-0/stm-1 toh and poh o verhead d ata i nput p ort 325 t able 291 t iming i nformation for the t ransmit stm-0/stm-1 toh and poh o verhead d ata i nput p ort ..................... 325 8.9 transmit vc-4 poh data input port .............. ................................................... .................................. 326 f igure 73. i llustration of t iming w ave - form of the t ransmit vc-4 poh d ata i nput p ort ............................................. 326 t able 292 t iming i nformation for the t ransmit vc-4 poh d ata i nput p ort .................................................. ................... 326 8.10 receive stm-0/stm-1 toh and poh data output po rt ................................................. ............... 327 f igure 74. i llustration of the t iming w ave - form of the r eceive stm-0/stm-1 toh and poh d ata o utput p ort ...... 327 t able 293 t iming i nformation for the r eceive stm-0/stm-1 toh and poh d ata o utput p ort ..................................... 327 8.11 receive vc-4 poh data output port ............. ................................................... ................................ 328 f igure 75. i llustration of the t iming w ave - form of the r eceive vc-4 poh d ata o utput p ort ..................................... 328 t able 294 t iming i nformation for the r eceive vc-4 poh d ata o utput p ort .................................................. ................. 328 8.12 ingress direction - add/drop port timing...... ................................................... ........................... 329 8.12.1 ingress direction - add port timing ......... ................................................... .............................................. 329 f igure 76. i llustration of the i ngress -d irection a dd p ort s ignals ................................................... ............................. 329 t able 295 t iming i nformation for the i ngress -d irection a dd p ort s ignals .................................................. ................... 329 8.12.2 ingress direction - drop port timing........ ................................................... ............................................. 330 f igure 77. i llustration of the i ngress -d irection d rop p ort s ignals ................................................... ............................ 330 t able 296 t iming i nformation for the i ngress -d irection d rop p ort s ignals .................................................. ................. 330 8.13 egress direction - add/drop port timing....... ................................................... ........................... 331 8.13.1 egress direction - add port timing.......... ................................................... ............................................... 331 f igure 78. i llustration of the e gress -d irection a dd p ort s ignals ................................................... .............................. 331 t able 297 t iming i nformation for the e gress -d irection a dd p ort s ignals .................................................. .................... 331 8.13.2 egress direction - drop port timing ......... ................................................... ............................................. 332
XRT86SH221 preliminary ix sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 f igure 79. i llustration of the e gress -d irection d rop p ort s ignals ................................................... ............................. 332 t able 298 t iming i nformation for the e gress -d irection d rop p ort s ignals .................................................. ................. 332 9.0 electrical characteristics ..................... ................................................... ............................ 333 t able 299 a bsolute m aximum r atings .................................................. ................................................... ............................... 333 t able 300: e1 r eceiver e lectrical c haracteristics .................................................. ................................................... ....... 334 10.0 background and protocols ...................... ................................................... ........................ 336 10.1 synchronous digtial hierarchy (sdh) standard .. ................................................... ................ 336 10.2 basic frame structure......................... ................................................... ............................................ 338 f igure 80. stm-n frame structure ................................................... ................................................... ................................. 338 11.0 reference documentation ....................... ................................................... ........................... 340 11.1 terminology ................................... ................................................... ................................................... .... 340 11.1.1 nomenclature ................................ ................................................... ................................................... .............. 340 11.1.2 signal name prefixes and suffixes........... ................................................... .............................................. 340 11.1.3 abbreviations ............................... ................................................... ................................................... ................ 340 o rdering i nformation ................................................... ................................................... ............ 343 p ackage d imensions 388 pbga ................................................... ................................................... ........ 343 r evisions ................................................... ................................................... .......................................... 344
preliminary XRT86SH221 4 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 1.0 pin descriptions 1.1 microprocessor interface pins 388 b all 568 b all p in n ame t ype d escription j26 k25 m23 k26 l25 m26 n25 p26 p24 r25 r24 t25 r23 u25 v25 u24 y26 u23 l30 m29 m30 n28 n29 p29 r30 r27 r28 t29 t27 u29 u28 v29 w30 w29 v27 aa30 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 i address input pins these address input pins are used for the microproc essor interface to the XRT86SH221. for timing information, please r efer to the tim- ing diagrams in the electrical specifications secti on of this datasheet. l24 l26 n23 n26 r26 u26 v26 w26 n27 p26 p27 r29 t30 t26 u27 u26 d7 d6 d5 d4 d3 d2 d1 d0 i/o bi-directional data bus pins these bi-directional data bus pins are used for the microprocessor interface to the XRT86SH221. for timing information , please refer to the timing diagrams in the electrical specificat ions section of this datasheet. t24 v30 ale / as i address latch enable / address strobe the function of this input pin depends on the micro processor inter- face mode. see the microprocessor section for timin g diagrams. t26 u30 cs i chip select input m24 n30 int o interrupt request output this active-low output signal will be asserted any time the XRT86SH221 is requesting interrupt service from the microproces- sor. n ote : this output pin is open-drain and requires a 10k w pull-up resistor. t23 v28 rd / ds / we i read strobe / data strobe the function of this input pin depends on the micro processor inter- face mode. see the microprocessor section for timin g diagrams. w25 y30 wr / r/w i write strobe / read-write operation identifier the function of this input pin depends on the micro processor inter- face mode. see the microprocessor section for timin g diagrams.
XRT86SH221 preliminary 5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 p25 r26 rdy / dtack / ta o ready or dtack output the function of this output pin depends on the micr oprocessor interface mode. see the microprocessor section for timing dia- grams. p2 p1 reset i hardware reset it is recommended to initiate a hw reset upon power up before configuring the device. this pin must be pulled "lo w" for a mini- mum of 10 m s to activate the reset circuitry. during a hw rese t, all outputs will be tri-stated and all on-chip register s will be reset to their default values.note: this pin has an internal 10k w pull-up resistor. p23 t28 pclk i microprocessor interface clock input this input clock signal is only used for the synchr onous micropro- cessor interface modes. this pin is ignored in the asynchronous microprocessor interface mode.note: the input frequ ency range of pclk is 66mhz. ac3 ab3 aa4 af3 ag2 ah1 ptype2 ptype1 ptype0 i microprocessor type select inputs these input pins are used to select the microproces sor mode according to the following table: n24 p30 dben i data bus enable this active-low input pin is used to enable the bi- directional data bus. to disable the data bus, this pin must be pull ed "high". for normal operation, this pin should be pulled "low". r3 p4 t5 t3 ext_int_1 ext_int_0 i external interrupt input [1:0] these pins can be used to force an interrupt reques t to the micro- processor by pulling either of these two pins "high ". the interrupt will be generated on the int output pin. n ote : if not used, these pins should be pulled "low". m25 p28 blast i reserved this pin can be left floating or tied to ground. 1.1 microprocessor interface pins 388 b all 568 b all p in n ame t ype d escription 000 ptype[2:0] 111 101 001 microprocessor interface mode mpc86x power pc 403 motorola asynchronous intel asynchronous
preliminary XRT86SH221 6 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 1.2 boundary scan and other test pins 388b all 568b all p in n ame t ype d escription jtag test pins d2 f4 tck i test clock input this pin is used for the boundary scan clock input. for normal operation, this pin should be pulled "low". d3 h6 tdi i test data input this pin is used for the boundary scan input data s ignal. for normal operation, this pin should be pulled "low". e4 e4 tdo o test data output this pin is used for the boundary scan output data signal. c2 c2 tms i test mode select this pin is used for the boundary scan test mode se lect input sig- nal. for normal operation, this pin should be pulle d "high". f4 g5 trst i test mode reset this pin is used for the boundary scan reset input signal. for nor- mal operation, this pin should be pulled "high". analog continuity and test pins p3 r4 testmode i for factory use only for normal operation, this pin must be pulled "low" . m3 l1 scan_mode i for factory use only for normal operation, this pin must be pulled "low" . ae2 ad5 scan_enb i for factory use only for normal operation, this pin must be pulled "low" . b15 a15 c15 e15 atp_ring1 atp_tip1 i/o analog test point - tip/ring 1 these pins along with the tms and tck boundary scan pins are used to perform continuity checks between the ttip/ tring and rtip/rring pins associated with e1 channels 0 throu gh 13. n ote : if not used, these pins should be left floating. af14 ae14 af15 aj14 atp_ring2 atp_tip2 i/o analog test point - tip/ring 2 these pins along with the tms and tck boundary scan pins are used to perform continuity checks between the ttip/ tring and rtip/rring pins associated with e1 channels 14 thro ugh 20. n ote : if not used, these pins should be left floating. c14 ad14 d15 ah14 analog1 analog2 o for factory use only these pins should be left floating a13 ac14 a14 ag14 sense1 sense2 o for factory use only these pins should be left floating
XRT86SH221 preliminary 7 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 1.3 general purpose input and output pins 388 b all 568 b all p in n ame t ype d escription gpio pins f3 e2 c1 h4 ad2 ac2 ae1 y4 h5 d2 g4 c1 ac5 ad4 ae3 af2 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 i/o general purpose i/o each of these pins can be configured to function as either a general purpose input or output pin by programming the gpio registers out- lined in the register map. one register is used to set the direction of each pin, while the other register is used to read/ write the value of each pin dependent on its direction. n ote : if not used, these pins should be left floating. 1.4 timing and clock signals 388 b all 568 b all p in n ame t ype d escription timing and clock pins g4 e3 mclk i master clock pll reference input clock this input functions as the reference input pin to the pll master clock and can accept any of the following signals b y program- ming the appropriate internal register. 2.048 / 4.096 / 8.192 / 16.384 mhz. a1 f5 ext_osc_enb i external oscillator enable this pin must be pulled "low". r2 r1 ext_osc i external oscillator this pin must be pulled "low".
preliminary XRT86SH221 8 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu r1 r3 tx51_19mhz i transmit stm-0/stm-1 timing reference input the function of this pin depends upon which mode th e XRT86SH221 has been configured to operate in. sdh over serial interface (stm-0 only) in this case, the XRT86SH221 will be configured to transmit data at a rate of 51.84mhz on the system side serial int erface. pro- vide a 51.84mhz clock signal to this pin. the trans mit stm-0 poh and soh processor blocks will use this clock si gnal as its timing reference. sdh over telecom bus interface in this case, the XRT86SH221 will be configured to output either an stm-0 or stm-1 signal via the transmit stm-0/stm -1 tele- com bus interface. provide a 19.44mhz clock signal to this pin for stm-1 or a 6.48mhz clock for stm-0 applications . the transmit stm-0/stm-1 poh and soh processor blocks w ill use this clock signal as its timing reference. n4 p5 txsbfp_in_out i/o transmit system bus frame pulse input / output the direction of this frame pulse is determined by whether the XRT86SH221 is the master of slave device in stm-1 s hared telecom bus applications whereby three voyager-lite devices are connected together. if the XRT86SH221 (along with two other XRT86SH221 devices) is configured to exchange stm-1 data over a com- mon telecom bus, and this particular device is the master device - txsbfp_out: the master XRT86SH221 will pulse this output pin "h igh" when it outputs the very first a1 byte (of a given outbound stm-1 frame) via the transmit stm-1 telecom bus interface. this pin will be kept "low" at all other times. if the XRT86SH221 (along with two other XRT86SH221 devices) is configured to exchange stm-1 data over a com- mon telecom bus, and this particular device is the slave device - txsbfp_in: the transmit stm-1 soh processor block (within a gi ven slave device) can be configured to initiate its generatio n of a new out- bound stm-1 frame based upon an externally supplied 8khz clock signal to this input pin. the transmit stm-1 telecom bus interface will begin transmitting the very first by te of a given stm-1 frame, upon sensing a rising edge of the 8khz signal on this pin. 1.4 timing and clock signals 388 b all 568 b all p in n ame t ype d escription
XRT86SH221 preliminary 9 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 1.5 low speed line interface signals 388 b all 568 b all p in n ame t ype d escription e1 receive line interface signals ab23 ac21 ae21 ac17 ae17 ae11 af8 ac9 ac7 af1 b2 c6 a5 c10 a11 a18 c18 d19 c22 d24 e25 ag25 aj26 ag22 ah19 ak18 ah12 ak6 aj5 ak2 ae5 a1 a2 a5 d10 d12 e17 e18 c22 e23 f23 e27 rtip20 rtip19 rtip18 rtip17 rtip16 rtip15 rtip14 rtip13 rtip12 rtip11 rtip10 rtip9 rtip8 rtip7 rtip6 rtip5 rtip4 rtip3 rtip2 rtip1 rtip0 i receive e1 line input - positive polarity signal rtip and rring are differential analog input pins t hat receive standard e1 return-to-zero data, coupled through a 1:1 trans- former. the transformer blocks the dc line bias and allows the inputs to be level shifted to mid-power supply. ac24 ad22 ac19 ad18 af18 af10 ae8 ad8 af2 ad3 d4 d7 d9 a8 b11 b18 b20 a24 c23 e24 c26 ae23 ah25 af21 af18 af17 aj11 aj7 af9 ag6 ae4 b1 b3 b6 e11 a10 a20 c20 d21 c26 d26 d28 rring20 rring19 rring18 rring17 rring16 rring15 rring14 rring13 rring12 rring11 rring10 rring9 rring8 rring7 rring6 rring5 rring4 rring3 rring2 rring1 rring0 i receive e1 line input - negative polarity signal rtip and rring are differential analog input pins t hat receive standard e1 return-to-zero data, coupled through a 1:1 trans- former. the transformer blocks the dc line bias and allows the inputs to be level shifted to mid-power supply.
preliminary XRT86SH221 10 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu ae26 y23 af27 ag28 rclk_rec1 rclk_rec0 o recovered line clock output each of these pins can be internally routed to one of the 21 e1 recovered line clocks to be used as an output clock reference, selected by programming the appropriate registers. by default (or if the recovered line clock is not selected), these ou tput pins are tri- stated. e1 transmit line interface signals 1.5 low speed line interface signals 388 b all 568 b all p in n ame t ype d escription
XRT86SH221 preliminary 11 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 ae25 ac20 ac18 ad17 ae16 ae12 af9 ad9 ac8 ac6 d6 b6 d10 b10 a12 a17 a19 c19 a25 c24 d25 af23 ag23 aj23 ak19 ak17 af14 aj8 aj6 aj4 af4 e5 c5 c8 d11 a11 d17 b20 d20 c25 d25 c28 ttip20 ttip19 ttip18 ttip17 ttip16 ttip15 ttip14 ttip13 ttip12 ttip11 ttip10 ttip9 ttip8 ttip7 ttip6 ttip5 ttip4 ttip3 ttip2 ttip1 ttip0 o transmit e1 line output - posittive polarity signal ttip and tring are differential analog output pins that transmit standard e1 return-to-zero data. the amplitude of t he output pulse is half the nominal e1 standard and level shi fted to v cc /2 to allow for optimum pulse shaping capability. therefo re, it's neces- sary to couple these analog outputs to a 1:2 step-u p transformer to apply a gain of 2x. it is recommended to connect a 0.1 m f capacitor in series with each ttip signal. ad24 ae23 af23 ae19 ac15 ad12 ac11 af6 ae5 ad4 c4 a3 b7 b9 d13 c16 a20 c20 b24 b25 g23 aj27 af22 ak25 aj19 ah17 ak11 ag10 ak4 ah5 ah2 c3 f8 e10 b9 c12 c18 b21 a24 d24 e24 e26 tring20 tring19 tring18 tring17 tring16 tring15 tring14 tring13 tring12 tring11 tring10 tring9 tring8 tring7 tring6 tring5 tring4 tring3 tring2 tring1 tring0 o transmit e1 line output - negative polarity signal ttip and tring are differential analog output pins that transmit standard e1 return-to-zero data. the amplitude of t he output pulse is half the nominal e1 standard and level shi fted to v cc /2 to allow for optimum pulse shaping capability. therefo re, it's neces- sary to couple these analog outputs to a 1:2 step-u p transformer to apply a gain of 2x. 1.5 low speed line interface signals 388 b all 568 b all p in n ame t ype d escription
preliminary XRT86SH221 12 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 1.6 high speed serial interface 388 b all 568 b all p in n ame t ype d escription sdh receive serial interface t1 t1 rxstm0clk i receive stm-0 serial input clock the high speed system bus can be configured to oper ate over a standard parallel telecom bus or a serial interface . if the serial interface is enabled, the XRT86SH221 samples data o n the ris- ing edge of this input clock signal. t2 u1 rxstm0data i receive stm-0 serial input data apply the serial input data to this pin, and it can be sampled on either the rising edge or falling edge of the rxstm 0clk input pin. u1 u2 rxstm0frame i receive stm-0 serial frame pulse this input pin should be connected to the frame pul se to indi- cate when the first bit of the current stm-0 frame occurs if con- nected to an external device, where this option is available. r4 u5 rxstm0los i receive stm-0 serial loss of signal if the high speed serial interface is connected to an external liu (line interface unit), then this input signal can b e connected to the los output pin from the liu. sdh transmit serial interface n2 p3 txstm0clk o transmit stm-0 serial output clock the high speed system bus can be configured to oper ate over a standard parallel telecom bus or a serial interface . if the serial interface is enabled, then the XRT86SH221 updates d ata on the rising edge of this output clock signal. the source of this clock can be a buffered clock derived from the recovered line clock in loop timing mode, or buffered from the internal mas ter clock in local timing mode. n1 r5 txstm0data o transmit stm-0 serial output data the serial output data can be updated on either the rising edge or falling edge of the txstm0clk output pin. p1 p2 txstm0frame o transmit stm-0 serial frame pulse this output frame pulse is used to indicate when th e first bit of the current stm-0 frame is transmitted if connected to an exter- nal device, where this option is available.
XRT86SH221 preliminary 13 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 1.7 high speed telecom bus interface 388 b all 568 b all p in n ame t ype d escription sdh receive telecom bus interface t3 v2 rxd_clk i receive stm-0/stm-1 telecom input clock the high speed system bus can be configured to oper ate over a standard parallel telecom bus or a serial interface . if the telecom bus is enabled, then all telecom bus signals are sa mpled on the rising edge of this input clock. this clock should be 6.48mhz for stm-0 or 19.44mhz for stm-1. v2 v5 rxd_dp i receive stm-0/stm-1 telecom data polarity this input pin can be configured to operate as the even or odd parity value of either the receive telecom data bus rxd_d[7:0] or the payload indicator rxd_pl and frame pulse rxd_c1j1v1_fp. n ote : this pin should be pulled "low" if the part is conf igured for re-phase on. u2 v3 rxd_pl i receive stm-0/stm-1 telecom payload indicator this input pin is used to indicate when payload byt es within an stm-0/stm-1 frame are being processed. this pin sho uld be pulled "high" for the entire duration of the payloa d bytes, and pulled "low" at all other times. t4 w3 rxd_alarm i receive stm-0/stm-1 telecom alarm status this input pin should be pulled "high" correspondin g to any stm-0/vc-3 signal that is carrying either the au-ai s or tu-ais indicator. at all other times, this pin should be p ulled "low". if this pin is pulled "high", the XRT86SH221 will automatic ally declare the au-ais or tu-ais defect for that particular vc- 3. v1 y1 rxd_c1j1v1_fp i receive stm-0/stm-1 telecom frame pulse the XRT86SH221 can be configured for re-phase on or re- phase off, meaning that frame synchronization can b e externally supplied to this input pin, or the XRT86SH221 can g ain frame synchronization from the incoming data. re-phase off this pin is ignored and can be tied to ground or le ft floating. re-phase on this pin should be pulled "high" during the c1 byte , j1 byte, and v1 byte. at all other times, this pin should be pul led "low". n ote : when 3 XRT86SH221 chips share the telecom bus in a master/slave mode, the c1 bytes must be aligned on all three input pins. the j1 and/or v1 bytes do not hav e to be aligned. y3 ac1 ab1 aa1 y2 w2 w1 u3 ae1 ad1 aa4 ac1 ab2 ab1 aa2 y3 rxd_d7 rxd_d6 rxd_d5 rxd_d4 rxd_d3 rxd_d2 rxd_d1 rxd_d0 i receive stm-0/stm-1 telecom input data bus these input pins are sampled on the rising edge of the receive telecom input clock rxd_clk. the msb of the data bu s is bit 7, and the lsb is bit 0.
preliminary XRT86SH221 14 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu sdh transmit telecom bus interface n3 m1 txd_clk o transmit stm-0/stm-1 telecom output clock the high speed system bus can be configured to oper ate over a standard parallel telecom bus or a serial interface . if the telecom bus is enabled, then all telecom bus signals are up dated on the falling edge of this output clock. the source of th is clock can be a buffered clock derived from the recovered line cloc k in loop tim- ing mode, or buffered from the internal master cloc k in local tim- ing mode. this clock should be 6.48mhz for stm-0 or 19.44mhz for stm-1. l2 l2 txd_dp o transmit stm-0/stm-1 telecom data polarity this output pin can be configured to operate as the even or odd parity value of either the transmit telecom dat a bus txd_d[7:0] or the payload indicator txd_pl and fram e pulse txd_c1j1v1_fp. m1 n3 txd_pl o transmit stm-0/stm-1 telecom payload indicator this output pin is used to indicate when payload by tes within an stm-0/stm-1 frame are being transmitted. this pin w ill be pulled "high" for the entire duration of the payloa d bytes, and pulled "low" at all other times. k1 k1 txd_alarm o transmit stm-0/stm-1 telecom alarm status this output pin will be pulled "high" corresponding to any stm-0/ vc-3 signal that is carrying either the au-ais or t u-ais indica- tor. at all other times, this pin will be pulled "l ow". m2 m2 txd_c1j1v1_fp o transmit stm-0/stm-1 telecom frame pulse the XRT86SH221 can be configured for re-phase on or re- phase off, meaning that frame synchronization can b e externally provided to the system or act as a simple frame pul se. re-phase off this pin is pulled "high" during the a1 byte. at al l other times, this pin is pulled "low". re-phase on this pin is pulled "high" during the c1 byte, j1 by te, and v1 byte. at all other times, this pin is pulled "low". n ote : when 3 XRT86SH221 chips share the telecom bus in a master/slave mode, all three chips will output this signal. h2 k3 l4 j2 j1 k2 l3 m4 g2 j3 h2 g1 j2 h1 j1 k2 txd_d7 txd_d6 txd_d5 txd_d4 txd_d3 txd_d2 txd_d1 txd_d0 o transmit stm-0/stm-1 telecom output data bus these output pins are updated on the rising edge of the transmit telecom output clock txd_clk. the msb of the data b us is bit 7, and the lsb is bit 0. 1.7 high speed telecom bus interface 388 b all 568 b all p in n ame t ype d escription
XRT86SH221 preliminary 15 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 1.8 high speed section and path overhead bus 388 b all 568 b all p in n ame t ype d escription receive section and path overhead extraction bus v3 aa3 rxoh o receive soh/poh data output port the extracted soh/poh overhead bytes will be update d on this output pin on the falling edge of rxohclk. therefor e, rxoh should be sampled using the rising edge of rxohclk. y1 w5 rxohclk o receive soh/poh overhead clock output this output clock signal is used as the timing refe rence for the receive overhead extraction bus. this clock will up date all out- put extraction bus pins on its falling edge. v4 y5 rxohframe o receive soh/poh overhead frame boundary indicator the receive soh/poh data output port will pulse thi s output pin "high" for one period of rxohclk, coincident to whenever it is extracting the very first bit of the stm-0/stm-1 frame in the section overhead (a1) and the very first bit of the path over- head (j1). if rxpoh_ind is "low" during this frame pulse, then that bit is a1. if rxpoh_ind is "high" during this frame pulse, then that bit is j1. this pin will be pulled "low" at all other times. u4 y4 rxohvalid o receive soh/poh overhead data valid indicator this output pin will be pulled "high" when the extr acted soh and poh bytes are ready to be sampled from the overhead bus. this pin will be pulled "low" at all other times. if rxp oh_ind is "low" while rxohvalid is "high", then soh is valid. if rx poh_ind is "high" while rxohvalid is "high", then poh is valid . this pin will be pulled "low" at all other times. w3 ab3 rxpoh_ind o receive poh indicator the receive path overhead indicator will pull "high ", coincident to whenever it is extracting path overhead data via the rxoh output pin. conversely, this pin will pull "low", c oincident to whenever it is extracting section overhead data via the rxoh output pin. this pin will be updated on the falling edge of rxo- hclk. transmit section and path overhead insertion bus k4 e1 txohen o transmit soh/poh overhead port enable output the state of this output pin determines the time pe riod when the XRT86SH221 can accept soh/poh overhead bytes. the o ver- head insertion bus is active when this pin is pulle d "high". g2 f2 txoh i transmit soh/poh data input port if the system side terminal equipment intends to in sert its own value for a given overhead soh or poh byte into the outbound stm-0 or stm-1 data-stream, then the system side te rminal equipment is expected to apply the overhead bytes t o this input pin while asserting the txohins input pin. this inp ut pin is sam- pled upon the rising edge of txohclk. g1 h3 txohclk o transmit soh/poh overhead clock output this output clock signal is used as the timing refe rence for the transmit overhead insertion bus. this clock will sa mple all input insertion bus pins on its rising edge.
preliminary XRT86SH221 16 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu j3 j4 txohframe i/o transmit soh/poh overhead frame boundary indicator the transmit soh/poh data input port will pulse thi s output pin "high" for one period of txohclk, coincident to whe never it is processing the very first soh byte of a given outbo und stm-0/ stm-1 frame in the section overhead (a1) and the ve ry first bit of the path overhead (j1). if txpoh_ind is "low" du ring this frame pulse, then that bit is a1. if txpoh_ind is " high" during this frame pulse, then that bit is j1. this pin wil l be pulled "low" at all other times. h1 f1 txohins i transmit soh/poh overhead insertion input if the system side terminal equipment intends to in sert its own value for a given overhead soh or poh byte into the outbound stm-0 or stm-1 data-stream, then this input pin sho uld be pulled "high" coincident with the soh or poh bytes. this input pin is sampled upon the rising edge of txohclk. f1 k5 txpoh_ind i/o transmit poh indicator the transmit soh/poh data input port will toggle an d hold this output pin "high", coincident to whenever it is rea dy to accept poh data via the txoh input pin. conversely, this p in will hold this pin "low", coincident to whenever it is ready to accept soh data via the txoh input pin. this pin will be updat ed on the fall- ing edge of txohclk as an output (or sampled on the rising edge as an input). 1.9 high speed tu poh overhead bus 388 b all 568 b all p in n ame t ype d escription receive tu poh extraction bus w4 aa5 rxtupoh o receive tu poh data output port this output pin will output the contents of the vc- 4 poh bytes within the incoming stm-1 data-stream. this output is updated on the falling edge of rxtupohclk. aa2 ab4 rxtupohclk o receive tu poh overhead clock output if the XRT86SH221 along with two other devices has been con- figured to operate in the stm-1/tug-3 mode, this ou tput clock signal is used as the timing reference for the rece ive vc-4 poh overhead extraction bus. this clock will update all output extrac- tion bus pins on its falling edge. ad1 ad2 rxtupo- hframe o receive tu poh data output port - frame boundary ou tput the receive tu poh data output port will pulse this output pin "high" for one period of rxtupohclk, coincident to whenever it is extracting the very first bit of the vc-4 poh . this pin will be pulled "low" at all other times. aa3 ab5 rxtupohvalid o receive tu poh data output port - overhead indicato r out- put this output pin will be pulled "high" when the extr acted vc-4 poh bytes are ready to be sampled from the overhead bus. this pin will be pulled "low" at all other times. 1.8 high speed section and path overhead bus 388 b all 568 b all p in n ame t ype d escription
XRT86SH221 preliminary 17 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 transmit tu poh insertion bus j4 d1 txtupohen o transmit tu poh overhead port enable output the state of this output pin determines the time pe riod when the XRT86SH221 can accept vc-4 poh overhead bytes. the over- head insertion bus is active when this pin is pulle d "high". f2 f3 txtupoh i transmit tu poh data input port if the system side terminal equipment intends to in sert its own value for a given vc-4 poh byte, then the system si de terminal equipment is expected to apply the overhead bytes t o this input pin while asserting the txtupohins input pin. this input pin is sampled upon the rising edge of txtupohclk. h3 h4 txtupohclk o transmit tu poh overhead clock output this output clock signal is used as the timing refe rence for the transmit overhead insertion bus. this clock will sa mple all input insertion bus pins on its rising edge. e1 g3 txtupo- hframe i/o transmit tu poh overhead frame boundary indicator the transmit tu poh data input port will pulse this output pin "high" for one period of txtupohclk, coincident to whenever it is processing the very first vc-4 poh byte. this pi n will be pulled "low" at all other times. d1 j5 txtupohins i transmit tu poh overhead insertion input if the system side terminal equipment intends to in sert its own value for a given overhead vc-4 poh byte, then this input pin should be pulled "high" coincident with the tu poh bytes. this input pin is sampled upon the rising edge of txtupo hclk. 1.9 high speed tu poh overhead bus 388 b all 568 b all p in n ame t ype d escription
preliminary XRT86SH221 18 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 1.10 power and ground pins 388 b all 568 b all p in n ame t ype d escription power supply b1, ab2, ab25, m15, p15, n15, a2, r15, m14, m13, p14, p13, n14, n13, r14, r13, m12, p12, n12, r12, g3 j6, ad3, ab25, e25, e20, p17, t17, r17, c4, u17, p16, p15, t16, t15, r16, r15, u16, u15, p14, t14, r14, u14, k6 1.8v digital - 1.8v digital power supply ac12, af15, ae20, b22, b14, a10, af13, d14 af12, ak13, ag19, b26, b15, b10, aj16, b17 1.8v analog - 1.8v analog power supply j23, p16, n16, l14, l13, t14, t13, p11, n11 j25, t18, r18, n16, aj30, n15, v16, v15, t13, r13 3.3v digital - 3.3v digital power supply ae4, ad7, af7, ad11, ad13, ad15, ae18, af21, ae22, ad23, f23, d22, c21, a22, d16, a16, b13, d12, b8, a4, b4, ad5, af3, ae7, ae9, ac13, af17, af19, ad19, af25, ac23, b26, d23, b23, a23, b19, d15, b12, a9, c9, d8, c5 ag4, ak3, ak5, ag11, ak12, ah16, aj18, af20, aj25, ag24, b29, f22, e22, b22, d18, a18, d13, a9, a7, a3, f7, ag3, af8, ah7, ah9, aj12, aj17, ag18, ak24, ae21, ak28, d27, b28, a28, e19, a21, a19, e13, c10, d9, d6, d4 3.3v analog - 3.3v analog power supply ground pins c3, e3, ab4, ac4, h23, m16, l16, l15, t16, t15, r16, m11, l12, l11, t12, t11, r11, ae3, ae6, ac10, ae10, af12, af16, ac16, af22, ad21, ac22, c25, a26, d20, d18, c17, b16, c13, c11, a7, c7, b3, ac5, ad6, af5, ad10, af11, ad16, af20, ad20, ae24, af26, f24, e23, d21, b21, d17, b17, c12, d11, a6, b5, d5, af4, ae15, af24, a21, a14, c8, ae13, c15 g6, d3, ac6, ad6, ad25, g25, p18, n18, n17, v18, v17, u18, p13, n14, n13, v14, v13, u13, af5, ag7, af10, ak7, ah13, ak16, ah18, ag21, ah24, ae22, f24, a29, f21, c21, c19, b18, b12, e12, a6, b4, d5, aj1, ae9, ag8, af11, ag13, ag17, ak20, aj24, ak27, ah26, f26, c27, b27, b23, d19, b19, b11, a8, b7, e7, b2, ae10, aj13, ah23, a22, a15, c7, af16, c17 gnd - ground
XRT86SH221 preliminary 19 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 no connect pins ab24, aa23, ad25, ac25, aa24, ad26, w23, aa25, y24, ac26, w24, v23, ab26, aa26, y25, v24, j25, l23, k24, h26, h25, g26, k23, j24, g25, f26, e26, h24, d26, g24, f25, l1 e2, l5, k4, m5, l4, k3, l3, n5, m4, m3, p4, n2, n1, r2, t4, t2, u3, u4, v1, w1, v4, w2, y2, w4, aa1, ac2, ac3, af1, ae2, aa6, ac4, ag1, ab6, af24, ak29, aj28, ah27, ag26, ae24, ag27, ah28, aj29, ae26, ak30, ac25, ae27, aj30, af28, ac26, ag29, ad27, ah30, ae28, af29, ac27, ag30, ad28, aa26, ae29, ab27, af30, ac28, ad29, y26, ab28, ac29, ad30, w26, y27, aa28, ab29, ac30, ab30, y28, v26, w27, aa29, y29, w28, n26, m28, l29, m27, k30, l28, k29, j30, k28, j29, h30, k27, l26, j28, h29, g30, f30, h28, j27, k26, g29, e30, f29, g28, k25, j26, e29, f28, g27, h26, c30, d29, e28, f27, h25, g26, b30, c29, a25, n4, af25, af26, ad26, ah29, aa25, ab26, ae30, aa27, m26, l27, h27, d30, ah3, ae7, aj2, af6, ak1, ag5, ah4, ae8, af7, aj3, ah6, ah10, aj9, ak8, ak9, aj10, ag12, af13, ah11, ak10, ag16, ak15, aj15, ah15, ag15, ak14, aj20, ak21, ah20, aj21, ak22, af19, ag20, ah21, aj22, ak26, b14, c14, d14, a13, e14, b13, c13, a12, c9, d23, a27, c24, e21, b25, d22, a26, c23, b24, a23, a17, d16, c16, b16, a16, c11, f10, e9, d8, a4, b5, c6, d7, f9, e8, e6, e16, a30 nc - no connect 1.10 power and ground pins 388 b all 568 b all p in n ame t ype d escription
preliminary XRT86SH221 20 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 2.0 applications and physical interface general over view the XRT86SH221 (voyager-lite) is a highly integrate d, monolithic device designed for cost-sensitive sd h to pdh mapper applications. voyager-lite supports all the framing, mapping and grooming functions require d for e1 aggregation to stm-1 via standard vc-12 to au-3 and au-4/tug-3 mapping protocols. the device generates and terminates all sdh regenerator sectio n, multiplexer section and path overhead including the low-order virtual container (vc) path overhead. e1 framing is transparent; therefore, the device neith er generates nor terminates the e1 frame. voyager-lite includes a standard telecom bus interf ace to an sdh (stm-0/stm-1) framer /mapper with sdh - to-pdh desynchronizer, vc-12/tu-12 mapper, vc-12 cr oss-connect and a 21-channel e1 short haul liu with integrated egress frame synchronizer for e1 bit-ret iming. voyager-lite also provides alarm and perform ance monitoring for all stm-1 and vc-12 overhead in comp liance with itu-t g.783 standards. section and path overhead may be inserted/extracted via serial inter faces provided in transmit and receive directions. the 21-channel e1 short haul liu provides line term ination and generation in compliance with g.703 standards, supporting e1 (2.048mbps) 75 w and 120 w applications. the liu receiver includes adaptive equalizer, clock and data recovery, and hdb3 decodi ng with performance monitoring of loss of signal, l ine code violations and excessive zeros. the liu transm itter includes hdb3 encoder, transmit pulse shaping and line driver. the liu also provides a half-duplex ji tter attenuator which may be applied in either the transmit or receive data path. e1 spans are mapped to vc-12/tu-12 via the virtual container (vc) and tributary unit (tu) mapper. vc-1 2 grooming support provided for both transmit and rec eive directions on a per e1 basis via the integrate d, full- duplex 21x21 vc-12 cross-connect. the sdh framer/ma pper supports generation and termination of stm-1 section and path overhead and also performs sdh to pdh desynchronization. a single voyager-lite performs mapping of 21 asynch ronous e1 spans to either vc-12/tu-12/tug-2/vc-3/au - 3/stm-0 or vc-12/tu-12/tug-2/tug-3/stm-0. vc mappin g to stm-1 requires (3) voyager-lite devices with one acting as "master" framer and two acting as "sl ave" framers. in this configuration, voyager-lite p erforms all the necessary framing, pointer processing and mappi ng functions required for mapping of 63xe1 spans to either vc-12/tu-12/tug-2/vc-3/au-3/stm-1 or vc-12/tu-12/tu g-2/tug-3/vc-4/au-4/stm-1. f igure 2. a pplication d iagram XRT86SH221 21 channel vc mapper ic XRT86SH221 21 channel vc mapper ic XRT86SH221 21 channel vc mapper ic xrt91l30 stm-1 transceiver ic 63 channels of e1 line signals shared transmit direction byte-wide bus, clocked at 19.44mhz stm-1 data via lvpecl shared received direction byte-wide bus, clocked at 19.44mhz
XRT86SH221 preliminary 21 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 2.1 physical interface voyager-lite consists of several physical interface s supporting the e1 line interface, stm-0/stm-1 lin e interface, sdh soh/poh and tu-poh overhead insertio n and extraction interfaces, timing and synchronization interfaces, microprocessor interfac e and jtag/testability interfaces. the diagram show n in figure 3 illustrates organization and applied nomenclature of these interfaces. f igure 3. s implified b lock d iagram of the p hysical i nterface physical interface ttip[20:0] tring[20:0] rclk[1:0] rtip[20:0] rring[20:0] test microprocessor sdh soh/ poh ins vc-4 poh ins sdh soh/ poh ext vc-4 poh ext receive telecom bus transmit telecom bus serial interface stm-0 ref clock 8khz 19.44mhz
preliminary XRT86SH221 22 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 2.2 telecom bus interface voyager-lite applications typically require transpo rt of stm-1 signals over optical networks. therefor e, voyager-lite provides a standard telecom bus which supports direct connection to stm-1 optical transce ivers such as the xrt91l30, stm-1 transceiver (cdr+serdes ). the signaling protocol defined for the voyager- lite telecom bus supports the multiplexing of stm-0 data streams required to create an aggregate stm-1 signal. however, the telecom bus also provides dire ct output of a single stm-0 data stream at 6.48mhz to support stm-0 mapping applications. ? the transmit telecom bus interface provides the in gress stm-0/stm-1 data stream output ? the receive telecom bus interface provides the egr ess stm-0/stm-1 data stream input the telecom bus interface consists of the following input/output signal. transmit telecom bus interface ?txa_d[7:0] 8-bit parallel telecom data bus ?txa_ck 19.44/6.48 mhz telecom bus clock ?txa_pl payload location indicator ?txa_c1j1 c1/j1/v1 byte location indicator ?txa_dp telecom data bus parity indicator ?txa_alarm au-ais/tu-ais alarm indicator receive telecom bus interface ?rxa_d[7:0] 8-bit parallel telecom data bus ?rxa_ck 19.44/6.48 mhz telecom bus clock ?rxa_pl payload location indicator ?rxa_c1j1 c1/j1/v1 byte location indicator ?rxa_dp telecom data bus parity indicator ?rxa_alarm au-ais/tu-ais alarm indicator f igure 4. s implified b lock d iagram of the t elecom b us i nterface telecom interface bus txa_d[7:0] txa_ck txa_pl txa_c1j1 txa_dp txa_alarm rxa_d[7:0] rxa_ck rxa_pl rxa_c1j1 rxa_dp rxa_alarm
XRT86SH221 preliminary 23 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 2.3 stm-0 serial interface sdh frame synchronization and timing interface in addition to the parallel telecom bus, the high s peed interface has the option to transmit and recei ve data through an stm-0 interface. stm-1 is not supported with the serial interface. ? the transmit serial interface provides the ingress stm-0 data stream output ? the receive serial interface provides the egress s tm-0 data stream input the serial interface consists of the following inpu t/output signal. transmit serial interface ?txstm0clk transmit serial interface clock ?txstm0data transmit serial interface data ?txstm0frame transmit serial interface frame pulse receive serial interface ?rxstm0clk receive serial interface clock ?rxstm0data receive serial interface data ?rxstm0frame receive serial interface frame pulse ?rxstm0los receive serial interface loss of signal f igure 5. s implified b lock d iagram of the s erial p ort i nterface serial interface bus rxstm0clk rxstm0data rxframe rxlos txstm0clk txstm0data txframe
preliminary XRT86SH221 24 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 2.4 sdh frame synchronization and timing interface sdh section layer processing at the stm-1 level is managed by a combination of overhead processing performed in the "master" framer as well as through synchronization of the sdh framing engines within the "master" and "slave" framers. the "master" device s upports insertion and monitoring of b1 bip-8 overhe ad and also distributes an 8khz frame sync to the "slave" devices. the "slave" devices source this frame sync as the reference for all sdh framer/mapper blocks. in part icular, the sdh framing, scrambling and descramblin g blocks rely upon this frame sync to ensure the "mas ter" and "slave" devices remain synchronized at all times. the XRT86SH221 requires a 19.44mhz input clock refe rence for timing of the telecom bus, sdh framers, sdh overhead processors, vc-12 mapper and vc-12 cro ss-connects for stm-1 applications. the same 19.44mhz reference should be applied to all three v oyager-lite device when operating in stm-1 mapper m ode. in the case of stm-0 applications, the device will accept a 6.48mhz reference input. the sdh frame synchronization and timing interface consists of the following signals. ?tx51_19mhz transmit stm-1/stm-0 timing reference i nput ?txsbfp_in_out system frame pulse (frame synchroniz ation signal) f igure 6. s implified b lock d iagram of the sdh f rame s ynchronization sdh frame sync txsbfp_in_out tx51_19mhz
XRT86SH221 preliminary 25 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 2.5 sdh overhead add-drop interfaces sdh overhead add-drop interfaces provide access to the sdh regenerator section, multiplexer section an d path overhead. please note there is no external int erface providing access to the vc-12 low-order path overhead. these interfaces allow flexible insertion and extraction of overhead and alarm data, thereby enabling proprietary processing of the sdh frame. ? the transmit sdh soh/poh overhead interface allows insertion of regenerator section, multiplexer section and path overhead data within the transmit stm-1/stm-0 data stream. ? the transmit tu poh overhead interface allows inse rtion of low-order path overhead data within the transmit tu-12/vc-12 data stream. ? the receive sdh soh/poh overhead interface allows extraction of regenerator section, multiplexer section and path overhead data from within the rece ive stm-1/stm-0 data stream. ? the receive tu poh overhead interface allows extra ction of low-order path overhead data from within t he receive tu-12/vc-12 data stream. the sdh overhead insertion/extraction interfaces co nsist of the following signals. transmit sdh soh/poh insertion bus (txoh) ?txohclk transmit overhead clock ?txoh transmit overhead data ?txohenable transmit overhead bus enable ?txohframe transmit overhead frame boundary indicat or ?txohins transmit overhead insertion control ?txpohind transmit overhead soh/poh indicator f igure 7. s implified b lock d iagram of the sdh o verhead a dd -d rop i nterface sdh overhead add / drop interface txohclk txoh txohenable txohframe txohins txpohind txtupohclk txtupoh txtupohenable txtupohframe txtupohins rxohclk rxoh rxohframe rxohvalid rxpohind rxtupohclk rxtupoh rxtupohframe rxtupohvalid
preliminary XRT86SH221 26 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu transmit tu poh insertion bus (txtupoh) ?txtupohclk txtupoh clock ?txtupoh txtupoh data ?txtupohenable txtupoh bus enable ?txtupohframe txtupoh frame boundary indicator ?txtupohins txtupoh insertion control receive sdh soh/poh overhead extraction bus (rxoh) ?rxohclk receive overhead clock ?rxoh receive overhead data ?rxohframe receive frame boundary indicator ?rxohvalid receive valid indicator ?rxpohind receive overhead soh/poh indictor receive tu poh extraction bus (rxtupoh) ?rxtupohclk rxtupoh clock ?rxtupoh rxtupoh data ?rxtupohframe rxtupoh frame boundary indicator ?rxtupohvalid rxtupoh valid indicator 2.6 e1 short haul line interface voyager-lite's e1 short haul liu provides the physi cal interface for 75 w coax and 120 w twisted pair applications. with selectable 75 w /120 w internal termination and option for high impedance on both transmit and receive liu interfaces, the device supports 1:1 and 1+1 redundancy with hitless hot-swapping for coax and twisted pair designs with a single bill-of-material s. the e1 transmit driver and receive equalizer are designed specifically to meet g.703 e1 short haul transport requirements. the e1 short haul line interfaces consist of the fo llowing signals. transmit line output signals ?ttip[0:20] e1 transmit tip data ?tring[0:20] e1 transmit ring data receive line input signals ?rtip[0:20] e1 receive tip data ?rring[0:20] e1 receive ring data note: ttip/tring and rtip/ring pins are grouped in pairs such as ttip0/tring0.
XRT86SH221 preliminary 27 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 2.7 e1 timing interface timing support within the 21-channel liu includes s ourcing of an external reference input clock and re covery of the incoming receive e1 line clock. this referen ce clock input frequency should be either 2.048mhz, 4.096mhz, 8.192mhz, or 16.386mhz. the e1 liu includ es a master clock synthesizer which accepts this in put clock reference and derives a 2.048mhz reference fu nctions such as clock and data recovery as well as timing of the e1 transmit output data stream. the clock an d data recovery circuit recovers the incoming recei ve e1 line clocks, which can be multiplexed to one of the two dedicated output pins, rclk_rec[1:0]. either t he e1 liu reference clock input or the recovered receive e1 line clock may be used as the timing source for the transmit e1 data stream bit-retiming function. the e1 timing interface consists of the following s ignals. ?mclk 2.048/4.096/8.192/16.384mhz reference clock i nput ?rclk_rec[1:0] recovered e1 (receive) line clock ou tputs 2.8 microprocessor interface voyager-lite provides a standard microprocessor int erface supporting intel, motorola, powerpc and mips synchronous/asynchronous pio bus interfaces. the mi croprocessor interface provides an 18-bit address a nd 8-bit data bus interface for configuration, control , status monitoring with up to 66 mhz read/write ac cess. the device allows a noon-multiplexed address and data b us, supports reset-upon-read/write-clear for contro l of status registers and provides programmable interrup t signal. the microprocessor interface consists of the follow ing signals. ?a[0:17] 18-bit address bus ?d[7:0] 8-bit data bus ?ale/as address latch enable/address strobe ?cs chip select ?int interrupt ?rd/ds/we read strobe/data strobe/write enable ?rdy'/dtack/rdy/ta ready, dtack, or transfer acknow ledge ?reset hardware reset input ?mpclk microprocessor interface clock input ?wr'/rw write strobe/read-write operation identifie r ?ptype[2:0] microprocessor interface type selector ?dben/oe bi-directional data bus enable
preliminary XRT86SH221 28 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 3.0 functional description the XRT86SH221 includes the following functional bl ocks ingress data path functional blocks ?e1 receive liu plus clock and data recovery (rxe1l iu) ?transmit tu poh insertion bus (txtupoh) ?vc-12/tu-12 transmit low-order mapper and overhead processor (txlopohproc) ?vc-12 transmit cross-connect (txvc12xc) ?transmit sdh soh/poh insertion bus (txtpoh) ?sdh transmit mapper and path overhead processor (t xpohproc) ?sdh transmit framer and section overhead processor (txsohproc) ?transmit telecom bus (txtbus) egress data path functional blocks ?receive telecom bus (rxtbus) ?sdh receive framer and section overhead processor (rxsohproc) ?sdh receive mapper and path overhead processor (rx pohproc) ?sdh receive soh/poh overhead extraction bus (rxtpo h) ?vc-12/tu-12 receive low-order overhead processor ( rxlopohproc) ?receive tu poh extraction bus (rxtupoh) ?vc-12 receive cross-connect (rxvc12xc) ?e1 transmit frame synchronizer and bit-retimer (tx e1frm) ?e1 transmit liu (txe1liu) f igure 8. f unctional b lock d iagram e1 receive liu + cdr tx vc-4 poh insertion bus low order mapper + oh transmit cross connect transmit mapper + poh sdh soh/poh insertion bus transmit framer + soh transmit telecom bus e1 transmit liu rx vc-4 poh extraction bus low order mapper + oh receive cross connect receive mapper + poh sdh soh/poh extraction bus receive framer + soh receive telecom bus ingress egress tx frame sync + bit re-timer
XRT86SH221 preliminary 29 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 3.1 ingress data path functional blocks the ingress data path is defined as the flow of dat a from the e1 liu receiver input through the vc map per and sdh framer/mapper to the transmit telecom bus. the following sections describe the general functions a nd detailed features for each block within the ingress data path. 3.2 e1 receive liu (rxe1liu) ?loss of signal (rlos) according to itu-t g.775 and ets300233 ?internal impedance matching on receive for 75 w or 120 w ?power down on a per channel basis ?selectable crystal-less digital jitter attenuators (ja) with 32-bit or 64-bit fifo that can be select ed in the receive path ?receive inputs may be set to high impedance for pr otection or redundancy applications on a per channel basis ?r3 technology for 1:1 or 1+1 redundancy without re lays ?on chip digital clock and data recovery for high i nput jitter tolerance ?qrss, taos, and network loop codes for receive dia gnostics ?supports remote loop back modes 3.3 transmit low-order (tu) overhead insertion bus ( txtupoh) the sdh transmit low-order (tu) overhead insertion bus provides capability to receive the tu-12/vc-12 low-order path overhead (lopoh) from an external pr ocessor. data received by the txtupoh block may be optionally inserted into the outgoing tu-12/vc-12 o verhead during generation of the corresponding over head byte within the txlopohproc block. f igure 9. s implified b lock d iagram of the i ngress d ata p ath e1 receive liu + cd r tx vc-4 poh insertion bus low order mapper + oh transm it cross connect transmit mapper + poh sdh soh/poh insertion bus transm it fram er + soh transm it telecom bus ingress
preliminary XRT86SH221 30 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 3.4 vc-12/tu-12 transmit low-order mapper and overhe ad processor (txlopohproc) the vc-12/tu-12 transmit low-order overhead process or performs asynchronous mapping of e1 spans into tu-12/vc-12 payloads. the txlopohproc receives 21 i ndependent e1 data streams from the receive e1 liu block and maps these e1 spans to tu-12/vc-12. this block generates all the necessary low-order path overhead including functions supported within the v 5, j2, n2, and k4 bytes. the primary features of the txlopohproc block inclu de the following functions ?maps (21) independent e1 spans into tu-12/vc-12 pa yloads ?generates the tu-12/vc-12 low-order path overhead ?supports low-order path overhead generation includ ing v5, j2, n2, and k4 ?v5 overhead generations support includes: ?bip-2 parity ?low-order path signal label ?low-order path remote error indicator (lo-rei) ?low-order path remote failure indicator (lo-rfi) ?low-order path remote defect indicator (lo-rdi) ?j2 overhead generation supports low-order access p ath identifier (lo-api) messaging ?n2 overhead generation supports for low-order tand em connection monitoring (lo-tcm) ?k4 overhead support for low-order aps signaling ?generates vc-12 stuff bits, overhead bits, justifi cation opportunity bits, and justification control bits to support rate adaptation between the incoming e1 sig nals and the sdh transmit timing reference ?low-order path overhead may be optionally forced t o reflect values configured within the software register map or those received by the txtupoh inser tion bus. 3.5 vc-12 transmit cross-connect (txvc12xc) the vc-12 transmit cross-connect operates in parall el with the vc-12/tu-12 transmit low-order path overhead processor to support grooming of the ingre ss vc-12 paths. the txvc12xc block provides a 21x21 vc-12 cross-connect which performs grooming of the vc-12 signals to support rearrangement, or reorderi ng, of the e1 traffic received from the e1 line interfa ce before mapping within the stm-0/stm-1 payload. 3.6 transmit sdh soh/poh insertion bus (txoh) the sdh transmit soh/poh overhead insertion bus rec eives section and path overhead data from an intern al processor for the purpose of insertion within the c orresponding byte of the outgoing stm-0/stm-1 signa l. this block receives the section and path overhead from e xternal pins and provides this data to the txpohpro c and txsohproc.
XRT86SH221 preliminary 31 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 3.7 sdh transmit mapper and path overhead processor (txpohproc) the sdh transmit mapper and path overhead processor receives tu-12/vc-12 overhead and payload data stream from the txlopohproc block and maps this dat a to either vc-3/au-3 or tug-3/vc-4/au-4. the txpohproc block performs all the mapping and overhe ad generation functions required at the high-order path layer. the txpohproc provides fixed pointer generat ion with a pointer value of "522" and also supports b3 parity calculation/insertion and high-order path al arm generation. data received by the txoh block may be optionally inserted into the outgoing path overhead during generation of the corresponding overhead by te within the txpohproc block. the primary features of the txpohproc block include the following functions payload pointer overhead ?fixed payload pointer (h1, h2, h3) generation with user programmable value (default = "522") ?supports ndf insertion within h1/h2 pointer ?performs mapping of tu-12/vc-12 data streams into either vc-3/au-3 or tug-3/vc-4/au-4 ?supports insertion of alarm indication signal - pa th (au-ais or ais-p) based on alarm and defects detected within the incoming egress stm-0/stm-1 sig nal ?performs b3 parity calculation and insertion ?c2 signal label insertion ?remote defect indication - path (rdi-p) alarm inse rtion ?remote error indication - path (rei-p) alarm inser tion ?supports h4 tributary unit multiframe indicator in sertion ?f3 user channel overhead generation ?supports k3 aps signaling ?supports n1 high-order path tandem connection sign aling ?path overhead may be optionally forced to reflect values configured within the software register map or those received by the txoh insertion bus.
preliminary XRT86SH221 32 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 3.8 sdh transmit framer and section overhead process or (txsohproc) the sdh transmit framer and section overhead proces sor receives the data from the txpohproc and completes the multiplexing and overhead generation process to create the stm-0/stm-1 signal output to the transmit telecom bus. the txsohproc performs all th e overhead processing required for regenerator and multiplexer section. the block includes supports or a1a2 frame generation, b1/b2 parity calculation, s ection trace messaging, dcc messaging, and k1/k2 aps suppo rt. data received by the txoh block may be optionally inserted into the outgoing section overh ead during generation of the corresponding overhead byte within the txsohproc block. the primary features of the txsohproc block include the following functions compliant regeneration section overhead ?frame generation with the a1/a2 bytes with optiona l alignment to external 8 khz frame sync ?provides optional error mask for a1/a2 frame bit e rror generation ?optional support for generation of los and sef con dition ?scrambling ?insertion of j0 section trace message ?b1 parity calculation and insertion with optional error mask ?e1 orderwire and f1 user channel overhead insertio n ?data communication channels (dcc messaging) insert ion within d1-d3 and d4-d12 multiplexer section overhead ?b2 parity calculation and insertion with optional error mask ?k1/k2 signaling for aps, alarm indication and remo te device indication ?alarm indication signal - line (ais-l) alarm gener ation ?remote defect indication - line (rdi-l) alarm gene ration ?remote error indicator - line (rei-l) alarm genera tion ?alarm generation based on incoming upstream defect s and optional software/hardware control ?data communication channels (dcc messaging) insert ion within d4-d12 ?s1 processing for synchronization status monitor ?m0/m1 generation for reporting of b2 bit/block err or counts to upstream equipment ?e2 orderwire overhead insertion
XRT86SH221 preliminary 33 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 3.9 transmit telecom bus (txtbus) the transmit telecom bus provides the ingress data path stm-0/stm-1 physical interface for connection to an stm-0/stm-1 transceiver module, downstream processo r or backplane connection. ?stm-0 mode: 8-bit parallel bus operating at 6.48mh z ?stm-1 mode: 8-bit parallel bus operating at 19.44m hz the transmit telecom bus provides a physical interf ace between the optical transceiver module and voya ger- lite for the ingress data path. this bus operates a t 19.44mbps for stm-1 applications and 6.48mpbs for stm- 0 applications using an 8-bit parallel data bus. th e primary function of this block is transmission of data to the optical transceiver, or other upstream processor. d ata received from the sdh transmit framer and secti on overhead processor is sent out on the txtbus. stm-0 timeslots for the aggregate stm-1 signals are prev iously byte-aligned. therefore, the txtbus performs and st m-1 multiplex function in order to create the aggre gate stm-1 output signal. for stm-1 applications, the txtbus within the "slav e" devices will send the stm-0 time slot for the ap propriate stm-0. the txtbus within the 'master" device will s end the stm-0 for time slot "0". the result is a ti me domain multiplexing of stm-0 signals at the txtbus which c reates the aggregate stm-0 signal. the "master" dev ice monitors the txtbus data during the "slave" device output timeslots for the purpose of b1 parity calcu lation. the txtbus supports the following features: ?optional configuration for the txtbus clock polari ty (positive/negative polarity) ?optional parity calculation for either the data bu s only or the combination of the data bus, pl, c1j1 and alarm signals. ?optional configuration of the txtbus data parity p olarity (positive/negative polarity ?optional configuration of the txtbus c1j1 indicato r for frame phase indication, payload phase indication or both
preliminary XRT86SH221 34 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 3.10 egress data path functional blocks the egress data path is defined as the flow of data from the receive telecom bus input through the sdh framer/mapper and vc mapper to the e1 liu transmit output as shown below in figure 10 . the following sections describe the general function and detailed features for each block within the egress data pat h. 3.11 receive telecom bus (rxtbus) the receive telecom bus provides the physical inter face between the optical transceiver module and voy ager- lite for the egress data path. this bus operates at 19.44mbps for stm-1 applications and 6.48mpbs for stm- 0 applications using an 8-bit parallel data bus. th e primary function of this block is reception of da ta from the optical transceiver, or other upstream processor. d ata received by the rxtbus is byte-aligned and pass ed to the sdh receive framer and section overhead process or. for stm-1 applications, the rxtbus within the "slav e" devices will sense only the stm-0 time slot for the appropriate stm-0. the rxtbus within the 'master" d evice will sense all stm-0 time slots for the aggre gate stm-1 signal in order to support the appropriate mo nitoring of section overhead functions such as b1 p arity. the rxtbus supports the following features: ?optional configuration for the rxtbus clock polari ty (positive/negative polarity) ?optional parity monitoring for either the data bus only or the combination of the data bus, pl, c1j1 and alarm signals. ?optional configuration of the rxtbus data parity p olarity (positive/negative polarity ?optional configuration of the rxtbus c1j1 indicato r for frame phase detection, payload phase detection or both ?byte-alignment of incoming stm-0/stm-1 data ?automatic insertion of downstream ais-p based on i ncoming rxd_alarm pin status f igure 10. s implified b lock d iagram of the e gress d ata p ath e1 transm it liu rx vc-4 poh extraction bus low order mapper + oh receive cross connect receive mapper + poh sdh soh/poh extraction bus receive fram er + soh receive telecom bus egress tx frame sync + bit re-tim er
XRT86SH221 preliminary 35 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 3.12 sdh receive framer and section overhead process or (rxsohproc) the sdh receive framer and section overhead process or receives the stm-0/stm-1 data stream from the rxtbus and performs all the overhead processing req uired for regenerator and multiplexer section termination. the rxsohproc supports performance, de fect and alarm monitoring for all section overhead data. the rxsohproc allows user access to the incoming so h data through microprocessor accessed registers or via the receive sdh soh/poh overhead extraction bus (rxoh). the primary features of the rxsohproc block include the following functions regeneration section overhead (aka - section overhe ad) ?loss of signal alarm detection ?frame-alignment of a1/a2 bytes ?severely errored frame (sef), or out-of-frame (oof ) alarm detection ?loss of frame (lof) alarm detection ?descrambling ?detects j0 section trace message and provides indi cation of ?j0 section trace message: mismatch ?j0 section trace message: invalid ?b1 parity monitoring with signal degrade (sd) and signal fail (sf) alarm detection ?includes programmable thresholds for declaration o f sd and sf conditions ?extracts e1 orderwire and f1 user channel overhead ?extracts data communication channels (dcc messagin g) from d1-d3 and d4-d12 multiplexer section overhead (aka - line overhead) ?b2 parity monitoring with signal degrade (sd) and signal fail (sf) alarm ?includes programmable thresholds for declaration o f sd and sf conditions ?k1/k2 processing for aps, alarm indication and rem ote device indication ?detects aps failure indicated within the k1/k2 byt es ?alarm indication signal - line (ais-l) alarm detec tion ?remote defect indication - line (rdi-l) alarm dete ction ?extracts data communication channels (dcc) messagi ng from d4-d12 ?s1 processing for synchronization status monitor ?remote error indicator - line (rei-l) alarm detect ion ?m0/m1 processing for collection of upstream b2 bit /block error counts ?extracts e2 orderwire overhead regenerator and multiplexer section error counters: ?provides 32-bit saturating counter of oof/sef erro rs ?provides 32-bit saturating counter of lof errors ?provides 32-bit saturating counter of los errors ?provides 32-bit saturating counter of sd errors ?provides 32-bit saturating counter of sf errors ?provides 32-bit saturating counter of rdi-l errors ?provides 32-bit saturating counter of rei-l errors ?provides 32-bit saturating counter of bip-8 b1 err ors ?provides 32-bit saturating counter of bip-8 b2 err ors
preliminary XRT86SH221 36 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 3.13 sdh receive mapper and path overhead processor (rxpohproc) the sdh receive mapper and path overhead processor receives the path overhead and payload data stream from the rxsohproc and performs all the overhead pr ocessing required for high-order path termination. the rxsohproc supports performance, defect and alarm mo nitoring for all high-order path overhead data. thi s block also performs pointer interpretation and dema pping of the stm-0/stm-1 payload. the rxpohproc terminates the au-4/vc-3/tug-3/tug-2 or au-3/vc-3/t ug-2 overhead, and passes the tu-12/vc-12 mapped data to the receive tu-12/vc-12 low-order ov erhead processor. the block supports user access to the incoming high-order poh data through microproce ssor accessed registers or via the receive sdh soh/ poh overhead extraction bus (rxoh). the primary features of the rxpohproc block include the following functions compliant with itu-t payload pointer overhead ?interprets payload pointer (h1, h2, h3), performs payload extraction and provides monitoring for ?loss of pointer (lop) alarm detection ?new data flag (ndf) ?alarm indication signal detection (au-aisp) ?new data flag (ndf) ?positive and negative stuff events ?alarm indication signal - path (au-ais or ais-p) a larm detection high-order path overhead ?detects j1 path trace message and provides indicat ion of ?j1 path trace message: trace identifier mismatch - path (tim-p) ?j1 path trace message: invalid ?b3 parity monitoring ?c2 signal label monitoring within indication of in valid, unequipped, and payload label mismatch statu s ?remote defect indication - path (rdi-p) alarm dete ction ?remote error indication - path (rei-p) alarm detec tion ?supports h4 tributary unit multiframe indicator ?extracts f3 user channel overhead ?supports k3 aps signaling ?supports n1 high-order path tandem connection sign aling error counters include the following: ?provides 32-bit saturating counter of lop ?provides 32-bit saturating counter of ais-p errors ?provides 32-bit saturating counter of bip-8 b3 err ors ?provides 32-bit saturating counter of rei-p errors
XRT86SH221 preliminary 37 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 4.0 voyager-lite hardware architecture and algorithm s this section intends to provide a description of t he overall voyager-lite architecture and functions of each module inside the chip. the detailed information ab out each module will be addressed in the following subsections. figure 11 represents a simplified block diagram of this devi ce. f igure 11. v oyager -l ite a rchitecture m u x s-2-p p-2-s vt/tu telecom bus init s-2-p vt mapper stn-0/1 proc sync m u x p-2-s's 21 x rx e1 frame synchronizer e1 sh liu sync sync m u x m u x clk smooth m u x e1 sh liu s-2-p m u x clk smooth gapped 50mhz clock domain stm-0(51)/telecom(19) e1 clock domain e1 in ref clock/loop clock serial stm-0/1 or stm-0/1 telecom bus 21
preliminary XRT86SH221 38 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 4.1 multiplexing structure figure 12 shows the relationship between various multiplexin g elements that are defined and illustrates possible multiplexing structures. vc type vc bandwidth vc payload vc-12 2 240 kbit/s 2 176 kbit/s f igure 12. m ultiplexing structure stm-1 stm-0 c-12 vc-12 tu-12 tug-2 vc-3 au-3 tug-3 vc-4 au-4 aug-1 pointer processing multiplexing aligning mapping
XRT86SH221 preliminary 39 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 4.2 functional blocks the voyager-lite device is functionally, as well as architecturally, divided into the following blocks and modules: n transceiver interface n stm-0/1 transmit framer (tx transport overhead proc essor) n stm-0/1 transmit toh (transport overhead) interface n stm-0/1 receive framer (rx transport overhead proce ssor) n stm-0/1 receive overhead interface n stm-0/1 transmit pointer processor (tx path overhea d processor) n stm-0/1 transmit poh (path overhead) interface n stm-0/1 receive pointer processor (rx path overhead processor) n stm-0/1 receive poh (path overhead) interface n vt mapper n 21 port cross connect n e1 receive framing synchronizer n liu control interface n liu modules n microprocessor interface n interrupt controller n performance monitor the operations and functions of these blocks are di scussed in detail in the following sections. this s ection gives an overview of the operation of this device. 4.3 sdh transmit data flow the sdh transmit blocks allow flexible insertion of transport and path overhead bytes through both har dware and software. the blocks also perform primitive sdh tasks such as data scrambling, bip-8 calculation a nd insertion, and fixed stuff columns insertion. the b locks are used to transmit an sdh stm-1 stream with any legal concatenation composition. the location of th e spe within the stm-1 frame is fixed with a pointe r offset of 522, which results in the j1 byte immediately tr ailing the last z0 byte in the transport overhead. figure 13 shows the general structure of an sdh transmitter. as in the case of sdh receive blocks, the sdh transmit blocks are reusable blocks that are config ured to transmit any compositions of any stm-n stre am (3c and 1). the sdh transmit block consists of a transp ort section (txspoh_proc and txspoh_cont blocks) an d 5 path sections. the txspoh_cont path overhead block receives path o verhead data from both software and hardware and allows software to select the version that is forwa rded to the txspoh_proc path processor block. softw are can also specify actions on the spe data such as ais-p insertion and rdi-p insertion. the txspoh_proc block receives payload data from th e vt mapper interface and path overhead data from t he txspoh_cont block and performs a multiplexing funct ion using the location information from the txspoh_ proc transport processor block. the txspoh_proc block al so generates the h1/h2 pointer bytes and provides t hem on its output data port at the appropriate instance s in the transport overhead. since there can be mul tiple path blocks for a sdh transmitter, the txspoh_proc block only puts bytes onto its output data ports when th e current transmit time slot belongs to its path. otherwise, zeros are placed on the output data port. the data from all the txspoh_proc blocks are ored together before being f orwarded to the txstoh_proc block. the txstoh_cont transport control block receives tr ansport overhead data from both software and hardwa re and allows software to specify the version that is forw arded to the txstoh_proc block. software also speci fies actions such as ais-l insertion, los insertion, and bip-8 error insertions.
preliminary XRT86SH221 40 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu the txstoh_proc block accepts spe data from the txs poh_proc blocks and transport overhead data from th e txstoh_cont block. the txstoh_proc block generates transmit location signals and chooses from the appr opriate input data stream for each byte location in the fra me. the txstoh_proc also generates time advanced ve rsions of the location signals for the other sdh transmit blocks to facilitate pipelining. 4.4 sdh receive data flow the sdh receive blocks receive sdh stm-1 signals wi th various concatenation compositions and perform t he necessary transport and path overhead processing. s trobe signals are generated for downstream circuitr y to extract the payload data. figure 14 shows the general composition of an sdh stm-1 rece iver. the receiver consists of a transport section and a path section. the receive transport s ection consists of one rxstoh_proc block which find s frame synchronization, performs error checking, de-scramb les the data, contains one rxstoh_stat block which provides the register file for the sdh receive tran sport section, maintains some counters and buffers, and contains one rxstoh_cap block which captures all th e transport overhead bytes for possible processing by the software. the receive path section consists of 5 pa th blocks. each path block consists of one rxspoh_p roc block which does pointer processing and error check ing, one rxspoh_stat block which provides the regis ter file for the receive path section and maintains some cou nters and buffers, and one rxspoh_cap block which captures all the path overhead bytes for processing by software. the sdh receive (and transmit) blocks support a 32 bit internal data bus width. the wider data width allows the sdh receiver/transmitter to limit the internal clock speed to a reasonable number for hig h bandwidth stm-1 streams. the byte align block is an auxiliary block acting a s a simple barrel shifter to align the incoming byt es according to the rxstoh_proc block's requests. f igure 13. sdh t ransmitter g eneral s tructure txspoh_cont block txspoh_proc block txspoh_cont block txstoh_proc block or function hw toh data processor interface bus transmit frame location counters spe data from other path blocks software toh data payload data from vt mapper hw poh data path software poh data spe dat
XRT86SH221 preliminary 41 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 4.5 vt mapper the vtm vt/tu mapper block is designed to map e1 si gnals into an sdh vc-3/tug-3 which in turn can be mapped respectively into an stm-0 or into an stm-1. this reusable block provides all of the functions necessary to insert and drop any valid combination of up to 21 asynchronous e1signals to or from an st m-0 payload capacity or an sdh vc-3. on the stm-0/stm-1 side, the reusable block has an 8-bit data bus. this allows it to interface to the other blocks that will process the higher layers of overh ead. on the e1 side, this block has bit serial data inputs and outputs. the vtm contains built-in test pattern ins ertion and drop capabilities that allow end-to-end testing for initial setup or maintenance without the need for e xternal test equipment. built-in loopbacks on both sides provide maximum flexibility for use in a number of sdh or e1 products including terminal multiplexers, add/ drop multiplexers, or digital cross connects. a hig h-speed microprocessor interface and full user programmability for vt/tu slot insertion and drop c ontrol provide maximum flexibility for e1 configura tion. f igure 14. g eneral c omposition of a sdh stm-n r eceiver byte align rxstoh_proc rxspoh_proc rxspoh_stat rxspoh_cap rxstoh_stat rxstoh_cap de-scrambled data location signals shifted raw data sdh data internal processor interface bus path block status & control status & control 1 path block for each additional path
preliminary XRT86SH221 42 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu the e1 to sdh section shown in the top part of figure 15 , handles the deserialization of the up to 21 incom ing signals. it handles the vt path overhead (sdh: vc p ath overhead) processing and fixed stuff insertion to generate a byte-serial stream on the 8-bit mid bus ready to be processed by the path, line and section overhead processing blocks to produce an stm-0 or s tm-1 signal. the sdh to e1 section shown in the bottom part of figure 15 accepts a byte-serial stream on the mid bus, removes the fixed stuff and extracts the virtual tr ibutaries (sdh: tributary units) to create up to 21 e1 signals with gapped clocks. f igure 15. t op l evel b lock d iagram 21 e1 mkp : make payload to sdh tpg 21 e1 xtp : extract payload from sdh e1 test channel reference clocks generator to external jitter attenuators 19.44mhz software interface registers addr data sel dtack irq read loopbacks & rdi/rei/rfi clock domain boundary e1in e1
XRT86SH221 preliminary 43 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 4.6 interrupts and status an interrupt pin (int) is provided for microcontrol ler interface. this interrupt pin provides interrup ts in response to alarm conditions, error events, messages receive d, error counter overflows, synchronization indicat ion, and parity errors. the interrupt scheme is organized i n a hierarchical status reporting architecture to p rovide a means for a microcontroller to identify the source of interrupt. status registers record the latest s ituation of condition events. an interrupt will be generated i f the enable bit corresponding to a given status is set in the interrupt enable register. each block contains several sources of interrupts. these interrupts are first multiplexed at the block level. then the interrupts from different blocks are integrated to generate an interrupt signal on the int pin. th e multiplexing of these interrupts is thus at two lev els: 1. source level. 2. block level at the source level, interrupts may be individually enabled or disabled. all interrupts in a block are multiplexed to produce a block level interrupt. these block lev el interrupts may then be separately enabled or dis abled. figure 16 is a simplified block diagram of the status report ing hierarchy. f igure 16. i nterrupt h ierarchy block interrupt enable register block interrupt enable register utopia interrupt enable register e1 framer interrupt enable register poh interrupt enable register poh interrupt enable register atm/ppp interrupt enable register vt mapper interrupt enable register toh interrupt enable register toh interrupt enable register block interrupt status register block interrupt status register utopia interrupt status register interrupt status register poh interrupt status register poh interrupt status register atm/ppp interrupt status register vt mapper interrupt status register toh interrupt status register toh interrupt status register & & & & & or or or or or to m p interrupt pin (pint_l) . . . e1 framer
preliminary XRT86SH221 44 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 4.7 interrupt processing and control each time an interrupt occurs, a microprocessor can identify the source of the interrupt by searching through the status hierarchy. the search will cause the st atus register on the search tree to be read. readi ng of the leaf status register will clear the enable bit(s) a ssociated with the interrupting status bit(s) if th e enbclr bit in interrupt control register is set. this will pr event continuous interrupts to be generated once th e microcontroller services the status register. read ing of the leaf status register will also reset the status bit(s) if the reset upon read (rur) option in the interrupt c ontrol register has been enabled. otherwise, a writ e is required to clear the bit(s) in the status register s. to clear the bit(s) in the status registers, the microcontroller needs to write a mask (0 to mask and 1 to clear) to this register to identify the bit that it wants to clear. status polling the sdh framer supports status polling capability f or all status registers. the operation is executed by preceding a read of these registers with a write. when a one is written to a bit position, the read r egister will be updated with the current value and the status bit w ill be cleared. when a zero is written to a bit po sition, the read register will not be updated and the previous value will be held. this scheme allows an external microcontroller to individually poll certain bits w ithout disturbing the other bits in the register. 4.8 stm-0/1 receive transport processor rxstoh_proc block the rxstoh_proc block has an 8 bit internal interfa ce bus. the rxstoh_proc block performs the followin g functions: byte alignment, los detection, frame ali gnment, de-scrambling, bip processing, and line rdi and ais detection. the rxstoh_proc block also generates location signals for the rest of the sdh receive b locks. byte_align block the byte_align block acts as a barrel shifter which shifts the parallel sdh input stream according to requests from the framer in the rxstoh_proc block. figure 17 shows the functional diagram of the byte_align blo ck. f igure 17. byte_align b lock f unctional d iagram shifter raw data 32 32 32 32 bit shift count rxstoh_proc byte 1 byte 1 shifted data 5
XRT86SH221 preliminary 45 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 los detection the rxstoh_proc block monitors the incoming scrambl ed data for the absence of 1's. the sdh standard ha s the following two rules for handling los defects wh ich are observed by the rxstoh_proc block. an sdh ne shall monitor all incoming sdh signals (b efore de-scrambling) for an "all-zeros pattern," wh ere an all-zeros pattern corresponds to no light pulses for oc-n optical interfaces and no voltage transit ions for stm-0 and stm-1 electrical interfaces. a los defect shall be detected when an all-zeros pattern on the incoming sdh signal lasts 100 m s or longer. if an all-zeros pattern lasts 2.3 m s or less, a los defect shall not be detected. an sdh ne shall terminate a los defect when the inc oming signal has two consecutive valid framing alignment patterns and during the intervening time (one frame), no all-zeros pattern qualifying as a l os defect exists. the rxstoh_proc block allows the software to specif y the number of all zero bytes before a los defect is declared and clears the los defect when the conditi ons stated are satisfied. the rxstoh_proc block also monitors the lopc (loss of optical carrier) input which when asserted, caus es the rxstoh_proc block to automatically assert ais downs tream (this feature is programmable by software). t his feature is useful when the off-chip optical instrum ent has detected a loss of carrier but the amplifie r data output to the chip still contains random transitions. frame alignment the rxstoh_proc block monitors the incoming stream for a1 and a2 patterns to determine frame alignment . the following sdh standard rules concerning finding fra me alignment are observed by the rxstoh_proc block. n the a1 byte shall be set to '11110110' (hex f6) and the a2 byte shall be se to '00101000' (hex 28) in all stm-0s within an stm-n. n the framing pattern observed by an sdh ne shall inc lude a subset of the a1 and a2 bytes contained in the incoming stm-n electrical or oc-n signal. n an sef defect shall be detected when the incoming s ignal has a minimum of 4 consecutive erred framing patterns. the maximum sef detection time sh all be 625 m s for a random signal. n the framing algorithm used to check the alignment s hall be such that an sef defect is not detected more than an average of once every 6 minutes while the ber of the stm-n electrical or oc-n signal is 10 -3 . n once an sef defect has been detected, the sdh ne sh all terminate the sef defect upon detecting two successive error-free framing patterns. n all incoming sdh signals shall be monitored for lof . a sdh ne shall detect an lof defect when an sef defect on the incoming sdh signal persists for 3ms. n the sdh ne shall terminate an lof defect 1ms to 3ms after terminating the sef defect on the incoming sdh signal, if the sef defect is not (re)d etected before the lof defect is terminated. the rxstoh_proc block implements the optional 3ms i ntegration timer to deal with sef and lof defects. the integration timer consists of an sef timer and an i n-frame timer that operates as follows: the in-frame timer is activated (accumulates) when an sef defect is absent. it stops accumulating and is reset to zero when an sef defect is detected. the sef ti mer is activated (accumulates) when an sef is prese nt. it stops accumulating when the sef defect is terminate d. it is reset to zero when the sef defect is absen t continuously for 3ms (i.e., the in-frame timer reac hes 3ms). an lof defect is detected when the accum ulated sef timer reaches the 3ms threshold. once detected, the lof defect is terminated when the in-frame tim er reaches 3ms (24 frames). when sef is low (i.e., the framer currently has fra me alignment), the rxstoh_proc block allows the sof tware to specify the number of correct a1 fields that must b e followed by the same number of correct a2 fields for the framing pattern to be considered correct. when the rxstoh_proc is searching for frame (i.e., the sef d efect has been declared), all bits of all the a1 and a2 bytes must be correct in order for the a1 or a2 byte to be considered valid.
preliminary XRT86SH221 46 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu once a frame has been located, the rxstoh_proc bloc k outputs the current row, column, and time slot of the de- scrambled data. note that for the 8-bit version of rxstoh_proc, a time slot is the same as an sts slot where as for the 32-bit version of rxstoh_proc, each time sl ot contains 4 sts slots (byte lanes). the software can also force the sef condition which causes the rxstoh_pro c to re-find frame. alternatively, the sdh framer also monitors a frame pulse input. when the frame pulse input is asserte d, the framer automatically assumes the current byte on th e input data bus is the first a1 byte. the software can force the sef condition in the fra mer in the rxstoh_proc block by writing a "1" to th e appropriate register file bit. this causes the rxst oh_proc block to declare an sef alarm and re-find f rame. the bit is cleared after the rxstoh_proc block has redi scovered frame alignment (after at least 1 frame) a nd the sef alarm has been removed. de-scrambling the rxstoh_proc de-scrambles all bytes of the incom ing stream except for thea1, a2, and j0/z0 bytes. t he following sdh standard rule is observed by rxstoh_p roc. de-scrambling can be disabled via software. sdh interface signals shall be scrambled (i.e., scr ambled at the transmitter and de-scrambled at the r eceiver) using a frame synchronous scrambler of sequence len gth 127, operating at the line rate. the generating polynomial for the scrambler shall be 1+x6+x7. the scrambler shall be reset to '1111111' on the most-s ignificant bit of the byte following the z0 byte in the nth st m-0 (i.e., the byte following the last z0 byte). th at bit and all subsequent bits to be scrambled shall be added, mod ulo 2, to the output from the x7 position of the sc rambler. the scrambler shall run continuously from that bit on throughout the remainder of the stm-n frame. bip processing the rxstoh_proc block calculates bip-8 over the per tinent bytes of the incoming stream for comparison with both the b1 and b2 fields of the transport overhead . the b1 and b2 values are calculated according to the following sdh standard rules: n the b1 byte in a line-side signal shall carry a bip -8 code, using even parity. the section bip-8 shall be calculated over all bits of the previous stm-n fram e after scrambling and placed in the b1 byte of the current stm-n frame before scrambling. n the b2 byte shall be provided in all stm-0s within an stm-n to carry a line bip-8 code, using even parity. the line bip-8 shall be calculated over all bits of the line overhead and the envelop capacity of the previous stm-0 frame before scrambling, and pla ced in the b2 byte of the current stm-0 frame before scrambling. the rxstoh_proc block outputs an error mask to the rxstoh_stat block after each comparison with b1/b2. note that only the first b1 byte of an stm-n stream cont ains the bip-8 bits. the second through the nth b1 bytes are all undefined. the number of b2 bytes is equal to the number of stm-0's within the stm-n signal. t wo memories are used in the b2 error code calculations . one memory is used to store the running value of the b2 error calculations. this memory is a 12x8/32 dual p ort ram with one port for reads and one port for wr ites. this is necessary because as the hardware is calcul ating the b2 code for each stm-0, it needs to store the new value into the memory and at the same time fetc h the current code for the next stm-0 from memory. the second memory is a single port 12x8/32 ram used to store the final b2 codes for all the stm-0's. this memory is read at the b2 byte locations for comparisons an d written into the a1 byte locations to store the f inal b2 codes for the previous frame. for the 8 bit version of the rxstoh_proc block, the b2 ram widths are 8 bits. for the 32 bit version of rxstoh_proc block, the b2 ram widths are 32 bits. line rdi and ais detection the rxstoh_proc block monitors the 3 least signific ant bits of the first k2 byte for rdi_l and ais_l d etection. the ais_l detection algorithm follows the following sdh standard rules: n lte shall detect an ais-l defect on the incoming si gnal when bits 6, 7, and 8 of the k2 byte contain t he '111' pattern in 5 consecutive frames n lte shall terminate the ais-l defect on the incomin g signal when bits 6, 7, and 8 of the k2 byte have any pattern other than '111' in five consecutive fr ames.
XRT86SH221 preliminary 47 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 n ote : the number of consecutive observations is 5. also, bits 6, 7 and 8 in the sdh standard refer to the le ast significant 3 bits. the rdi_l detection algorithm follows the f ollowing sdh standard rules: n lte shall detect an rdi-l defect on the incoming si gnal when bits 6, 7, and 8 of the k2 byte contains the '110' pattern in 5 to 10 consecutive frames n lte shall terminate the rdi-l defect on the incomin g signal when bits 6, 7, and 8 of the k2 byte have any pattern other than '110' in five to 10 consecut ive frames. downstream ais insertion the rxstoh_proc block will insert path ais in the d ownstream data when prompted by the rxstoh_stat blo ck. rxstoh_stat block the rxstoh_stat block has an 8 bit internal bus. th e rxstoh_stat block contains the status and control registers for the transport overhead blocks. in addition, the rxstoh_stat block monitors the s1, rei-l, and k1/k 2 fields of the transport overhead. the rxstoh_stat block also monitors the b1 and b2 error masks and accumulates the bit or word error events. synchronization status (s1) monitor the rxstoh_stat block extracts the synchronization status (s1) byte from the line overhead and monitor s it for change. the s1 byte is only defined for the first s tm-0 in an stm-1 signal. the extraction algorithm i s defined by the sdh standard as: n a change in the s1 synchronization status message s hall be detected if at least 8 consecutive samples (these may or may not be consecutive sdh frames) of bits 5-8 (least significant 4 bits) of the s1 byte have the same (new) value. the sampling rate shall be such that the maximum time to detect a change (assuming no transmission errors) is 1 second. n for s1 messages, if no validated synchronization st atus message is detected (e.g., due to transmission errors or the receipt of an undefined message) for a period of greater than 10 seconds, the ne shall consider the reference failed. the rxstoh_stat block monitors the s1 byte for 8 co nsecutive identical values after which the new valu e is stored in a register for access by software. the rx stoh_stat block also implements a counter for an un stable s1. this counter is incremented for each byte that differs from the previously received byte. an inval id s1 condition is declared when the s1 counter reaches 3 2. the s1 counter is cleared to 0 when 8 consecutiv e identical s1 bytes are received. upon detection of an invalid s1 condition, the software can then set up a 10s timer to detect for s1 reference failure. rei-l (m0/m1) monitor the m0/m1 field contains the line remote error indi cator (rei-l) count. for an stm-0 stream, the count is contained in the first rei-l byte (m0 byte) whereas for an stm-1 or higher stream, the count is contai ned in the third rei-l byte (m1 byte). the rxstoh_stat block i nterprets the rei-l field according to the followin g sdh standard rules: n lte terminating an oc-1 or stm-0 electrical signal shall set bits 5 through 8 of the m0 byte to indica te (to the upstream lte) the count of the interleaved- bit block errors that it has detected based on the bip- 8 (b2) byte. the error count shall be a binary numb er from zero (i.e., 0000) to 8 (i.e., 1000). the remaining seven values represented by the four rei- l bits (i.e., 1001 through 1111) shall not be transmitted, and shall be interpreted by receiving lte as zero errors. n lte terminating an oc-n or stm-n electrical signal (n greater than or equal to 3) shall set the m1 byt e to indicate (to the upstream lte) the count of the interleaved-bit block errors that it has detected u sing the b2 bytes. for values of n below 48, the error c ount shall be a binary number from zero to 8xn. the remaining possible values [i.e., 255-(8xn)] represe nted by the eight rei-l bits shall not be transmitt ed and shall be interpreted by the receiving lte as ze ro errors. for n equal to 48, the count shall be truncated at 255. the rxstoh_stat accumulates the rei-l counts in a 2 0 bit saturation counter. the count is transferred to a holding register and reset by software request. the rxstoh_stat also flags any non zero rei-l counts. the
preliminary XRT86SH221 48 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu software can configure the rxstoh_stat block to acc umulate either bit errors or error events. an error event is defined as any non-zero rei-l count. since 8000 frames are received each second and the maximum rei-l count of each frame is 255, the software should poll (and clear) the m1 counter at least once every 232/(8000x255) = 2105 seconds. k1/k2 monitor the rxstoh_stat block filters and captures the firs t k1 and k2 bytes of the stm-n stream for aps proce ssing by the software. the filtering is done based on the fo llowing sdh standard rule: n a new code on the received k1 and k2 bytes shall re place the current received code if it is received identically in five consecutive frames. in addition, rxstoh_stat also monitors the k1 byte for inconsistent aps byte error according to the fo llowing definition of the sdh standard. "an inconsistent aps byte occurs when no three (fiv e) consecutive k1 bytes of the last 12 successive f rames are identical, starting with the last frame contain ing a previously consistent byte." when an inconsistent aps byte occurs, a flag is set to notify the software. when a new k1/k2 code is detected, a flag is set to notify the software. b1 error monitor the rxstoh_stat block monitors the b1 error mask fr om the rxstoh_proc block and accumulates the error count in a 16 bit saturation counter. upon software reque st, the count is transferred to a holding register and reset. the software specifies whether to accumulate b1 err or bits or events where an error event is defined a s any non-zero b1 error mask received from the rxstoh_pro c block. a flag is set to notify the software whene ver a b1 error event occurs. since 8000 frames are received each second and the maximum b1 error count of each frame is 8, the coun ter will saturate after 232/(8000x8) = 67108 seconds b2/sd/sf error monitor the rxstoh_stat block accumulates the b2 error coun t using a 32 bit counter in the same manner as the b1 error counter. since 8000 frames are received each second and the maximum b2 error count of each frame is 384, the software should poll (and clear) the m1 co unter at least once every 232/(8000x384) = 1398 sec onds. in addition, the rxstoh_stat block monitors bip-2 c odes for signal fail (sf) and signal degrade (sd) conditions. the sd/sf monitoring is done using a di scretized sliding window protocol in which the slid ing window size is de-composed into 8 sub-intervals. sd /sf is declared if the total b2 error count of all the sub- intervals exceeds a given threshold. similarly, sd/ sf is cleared when the total b2 error count is belo w a given threshold. in addition, the user can specify a burs t tolerance threshold for each sub-interval. the b2 error count for each sub-interval is saturated at the burst tol erance threshold. the window size and thresholds fo r declaring and clearing sd/sf alarms are specified s eparately. the window size and thresholds for sd a nd sf are also specified separately. as a result, 4 slidi ng windows are needed. the sliding window is implem ented by the rxstoh_berm block, 4 of which are instantiated by the rxstoh_stat block. the setting and clearing of the sf and sd signals a dhere to the following sdh standard rules and recommendations: n loss of signal, loss of frame, ais-l defects, and a line ber exceeding 10 -3 on an incoming oc-n shall be detected as sf conditions on that line. n the ber threshold for an sf condition may be requir ed to be user-provisionable over the range of 10 -3 to 10 -5 n a ber exceeding the sd threshold on an incoming oc- n shall be detected as an sd condition on that line n the ber threshold for an sd condition shall be user -provisionable over the range of 10 -5 to 10 -9
XRT86SH221 preliminary 49 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 the rxstoh_stat block lets software specify the tim e interval over which to monitor the b2 error count s and the thresholds over/under which to set/clear the sf and sd conditions. sef force software can force the sef condition in the frame f inder in the rxstoh_proc block by writing a "1" to the appropriate register file bit. this causes the rxst oh_proc block to re-find frame. the bit is cleared after the rxstoh_proc block has rediscovered frame alignment (after at least 1 frame). section trace (j0) monitor the sdh standard has defined the j0 byte as a 1 byt e or 16 byte message in the following manner: this byte is used to transmit repetitively a sectio n access point identifier so that a section receive r can verify its continued connection to the intended transmitte r. within a national network, or within the domain of a single operator, this section access point identifier may use either a single byte (containing the code 0-255 ) or the access point identifier format as defined in clause 3/g.831. at international boundaries, or at the bo undaries between the networks of different operators, the fo rmat defined in clause 3/g.831 shall be used unless otherwise mutually agreed by the operators providin g the transport. a 16-byte frame is defined for the transmission of section access point identifiers where these confor m to the definition contained in clause 3/g.831. the first b yte of the string is a frame start marker and inclu des the result of a crc-7 calculation over the previous frame. the following 15 bytes are used for the transport of 1 5 t.50 characters (international reference version) requir ed for the section access point identifier. the 16 byte frame description is given in the table below: in the case of inter-working of equipment implement ing the stm identifier functionality and equipment employing the regenerator section trace function, t he latter shall interpret the pattern "0000001" in j0 as "regenerator section trace - unspecified". this uns pecified regenerator section trace can also be used if no use of the regenerator section trace is made. the rxstoh_stat block enables software to specify t he length of the j0 section trace message. this len gth could be 1 or 16 for sdh, and 64 should the sdh standard in the future specify the j0 byte as a section trac e byte. the software also specifies whether to look for an lf or a starting "1" bit when the rxstoh_stat block is trying to locate the start of the message. the software also specifies the number (3 or 5) of consecutive consis tent section trace messages that must be observed before it is accepted. an interrupt is generated when a new section trace message is accepted as valid. the valid section tra ce message is compared with an expected section trace message downloaded to memory by software. a j0 mismatch (j0_mis) flag is raised if the 2 messages are not identical. the rxstoh_stat block also imple ments a j0 unstable counter. the j0 unstable counter is inc remented for each byte that differs from the previo usly t able 1: 16- byte frame for t rail api d b yte # v alue ( bit 1, 2, ,8) 1 1 c1 c2 c3 c4 c5 c6 c7 2 0 x x x x x x x 3 0 x x x x x x x : : : 16 0 x x x x x x x n otes : 1. c1 to c7 is the result of the crc-7 calculation o ver the previous frame. c1 is the msb. the descript ion of this crc-7 calculation is given in annex b 2. 0xxxxxxx represents a t.50 character. .2
preliminary XRT86SH221 50 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu received byte. an invalid j0 condition is declared when the j0 unstable counter reaches 8. the j0 unst able counter is cleared to 0 when a valid j0 is accepted . the sdh receive section trace buffer uses a 128x8 s ingle port memory and a 64x8 single port memory. th e memories are organised as shown in figure 18 . the 128x8 single port ram has 2 segments: n one segment stores the current accepted trace messa ge n one segment stores the previous received trace mess age the 64x8 single port ram stores the expected trace message which is downloaded by the cpu. whenever a new trace message is accepted as valid, the valid message buffer and the previous message buffer swap in the sense that what used to be the v alid message buffer segment is now the segment for storing the previous received message and vice versa. the c pu downloads new expected trace messages to the new expected message buffer. since comparisons between the expected trace message buffer and the accepted trace message buffer are not valid when the cpu is downloading to the expected trace message buffer, t he j0 mismatch interrupt should be disabled during downlo ading of the expected trace message buffer. downstream ais insertion control the rxstoh_stat block can be configured to cause do wnstream ais insertion when any of the following conditions are detected: ais-l, los, lof, lopc, sd, sf, j0 mismatch, and j0 unstable. downstream ais insertion to the path section is done according to the following sdh rule: n lte shall generate ais-p downstream for the affecte d sts paths within 125 m s of detecting an ais-l defect (or a lower layer, traffic-related, near-end defect) or (if the sts pointer is processed) an lo p-p defect on the incoming signal, or the failure of st s pte supporting provisioned path origination functions. the ais-p shall be generated as all-ones in the h1, h2 and h3 bytes, and the entire sts spe. n lte shall deactivate the ais-p within 125 m s of terminating the defect that caused it to be se nt, or in the case of a local equipment failure, within 125 m s of clearing the failure or determining that stand by equipment has been switched in. lte that performs s ts pointer processing shall deactivate ais-p by constructing a correct sts pointer with a set ndf, followed by normal pointer operations, as well as ceasing to insert the all ones pattern in the sts s pe. lte that does not perform sts pointer processin g shall deactivate ais-p by ceasing the insertion of all ones in the h1, h2 and h3 bytes, and the sts spe. f igure 18. r eceive t race b uffer m emory j0 current expected message buffer 8h00 8h3f j0 current valid message buffer j0 previous received message buffer 8h00 8h3f 8h40 8h7f
XRT86SH221 preliminary 51 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 the software can enable or disable the insertion of path ais-p on detection of any of the aforemention ed conditions. if path ais insertion is necessary, the n an enable signal to the rxstoh_proc block is acti vated which causes the rxstoh_proc block to insert all ones in the pertinent bytes. rxstoh_cap block the rxstoh_cap block has an 8 bit internal interfac e bus. the rxstoh_cap block captures the contents o f the sdh overhead for up to 3 stm-0 slots and stores the m for access by the external processor. on a read a ccess from the processor interface, the bit rxstoh_cap bl ock accepts a 9 bit address of the form: xxxxxyyyy where xxxxx specifies the field number and yyyy specifies the time slot number of the 4 bytes that are reque sted. one 944x8 (stm-1) or 256x8 (stm-0) single port ram is used to capture and hold the sdh oh contents for the processor of each byte-slice module. the memory is divided into one 512 x 8 (only 432 is used) and one 432 x 8 segments. one segment captures the sdh over head bytes from the current frame while the other segment stores the transport overhead bytes from th e previous frame. the two segments are swapped afte r every frame in the sense that what used to be the c urrent sdh oh byte capture segment is now the holdi ng segment for the previous frame and vice versa. when the last sdh overhead byte of the current fram e has been written into memory, an interrupt is gen erated to notify the software. the contents of the sdh ove rhead memory will be preserved for one frame (i.e., until the next sdh oh capture generates an interrupt) for acc ess by the software. the captured sdh oh bytes are available to the proc essor via indirect memory registers. the addressing scheme used to access the sdh oh bytes is shown in table 2 . each access to a captured sdh oh byte consists of writing the corresponding address into the sdh oh capture indirect address register follow ed by a read/write to/from the sdh oh capture indirect data register. t able 2: a ddressing s cheme u sed to a ccess the sdh oh b ytes addr[9:2] byte 3 (msb) byte 2 byte 1 byte 0 (lsb) {5'h00, 2'h0} a1 (sts-0) a1 (stm-0) a1 (sts-2) a1 (stm-1 ) {5'h00, 2'h1} a1 (sts-4) a1 (sts-5) a1 (sts-6) a1 (sts-7 ) {5'h00, 2'h2} a1 (sts-8) a1 (sts-9) a1 (stm-00) a1 (stm- 01) {5'h00, 2'h3} unused unused unused unused {5'h01, 2'h0} a2 (sts-0) a2 (stm-0) a2 (sts-2) a2 (stm-1 ) {5'h01, 2'h1} a2 (sts-4) a2 (sts-5) a2 (sts-6) a2 (sts-7 ) {5'h01, 2'h2} a2 (sts-8) a2 (sts-9) a2 (stm-00) a2 (stm- 01) {5'h01, 2'h3} unused unused unused unused .. . .. . .. . .. . .. . {5'h1a, 2'h0} e2 byte 26 (stm-0) byte 26 (sts-2) byte 2 6 (stm-1) . . . . . {5'h1a, 2'h2} byte 26 (sts-8) byte 26 (sts-9) byte 26 (stm-00) byte 26 (stm-01) {5'h1a, 2'hc} unused unused unused unused .. .. .. .. ..
preliminary XRT86SH221 52 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu when this module is used for the stm-0 or stm-1 por t, the captured sdh overhead bytes are serialized and sent as outputs from the chip (with the exception o f the m0 byte which is replaced by the more useful m1 byte from the third stm-0). the bytes are multiplexed on to a single bit stream as shown in figure 19 . the rxoh, rxohframe, and rxohvalid signals are updated on the falling edge of rxohclk. when used on the stm-0/stm-1 side, the bytes captured are sent out t o the external interface through an 8-bit bus. f igure 19. r eceive t ransport o verhead i nterface t iming sdh overhead: clock and signal bits rxohclk rxohframe rxoh a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 j0 j0 j0 j0 j0 j0 j0 j0 note: rxpoh_ind is low for sdh oh drop -off. the most significant bit is transmitted first rxohclk rxohframe rxoh a1 a2 j0 b1 e1 f1 d1 d2 d3 h1 h2 h3 note: all the other sdh oh bytes from stm -0 #1 follow similarly with the exception of the m0 /m1 byte position which contains m1 from stm-0 #2 rather tha n m0. sdh overhead: clock and signal bytes rxohvalid rxohvalid
XRT86SH221 preliminary 53 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 stm-0/1 receive path processor rxspoh_proc block the pointer processing operation of the rxspoh_proc block is described by the following sdh standard r ules: n the pointer value shall be a binary number with a r ange of 0 to 782, and shall indicate the offset between the pointer word (the last byte of the h3 f ield) and the first byte of the sts spe. n a pointer increment operation shall be indicated by inverting the i-bits of the pointer word. the posi tive stuff byte shall appear immediately after the h3 by te in the frame containing the inverted i-bits. n a pointer decrement operation shall be indicated by inverting the d-bits of the pointer word. the h3 b yte shall be used as the negative stuff byte, (i.e., it is used to carry an spe byte in the frame containi ng the inverted d-bits). n the increment/decrement decision should be made at the receiver by a match of 8 or more of the 10 i- and d-bits to either the increment or decrement ind ication. n a normal ndf shall be indicated (during normal oper ation) by a '0110' code in the n-bits. the ndf shal l be set by inverting the n-bits to '1001'. the new a lignment of the sts pse shall be indicated by the pointer value accompanying the set ndf and takes ef fect at the offset indicated. n the decoding at the pointer processor shall be perf ormed by majority voting (i.e., the ndf shall be detected as being set if three or four of the n-bit s match the '1001' code). if a set ndf is detected, then the coincident pointer value shall replace the curr ent value at the offset indicated by the new pointe r value. n the first stm-0 within an stm-nc shall have a norma l pointer word n all subsequent stm-0s within the stm-nc shall have their pointer values (i.e., bits 7 through 16) set to all-ones, and their n-bits set to '1001' (i.e., set ndfs). n a pointer processor in an ne that is transmitting o r receiving an stm-nc spe shall perform the operations indicated by the pointer in the first st m-0 of the stm-nc on all n of the stm-0s in that st m- nc. n during normal operation, the pointer value locates the start of the sts spe within the sts envelop capacity. n any variation from the current pointer value shall be ignored unless a consistent new value is receive d three times consecutively, or the variation is one of the operations in rules 4, 5, or 6. n any consistent new value received three times in su ccession shall replace the current value at the off set indicated by the new pointer value. n if the pointer word contains the concatenation indi cator, then the operations performed on that stm-0 are identical to those performed on the first stm-0 within the stm-nc. rules 4 and 5 do not apply to t his pointer word. n if an increment is detected, then the byte followin g h3 shall be considered a positive stuff byte, and the current pointer value shall be incremented by one. n if a decrement is detected, then h3 shall be consid ered a negative stuff byte, and the current pointer value shall be decrement by one. n if a set ndf is detected, then the coincident point er value replaces the current value at the offset indicated by the new pointer value. n sts pte and lte that processes the sts pointer shal l monitor for lop-p. an lop-p defect shall be detected if a valid pointer is not found in n conse cutive frames (where 8 is less than or equal to n l ess than or equal to 10), or if n consecutive ndfs (oth er than in a concatenation indicator) are detected. an lop-p defect shall not be detected when lte is rece iving and relaying an all-ones sts pointer, or when sts pte is receiving pointers that qualify as those necessary to cause the detection of an ais-p defec t (i.e., three or more consecutive all-ones pointers) n sts pte and lte that processes the sts pointers sha ll terminate an lop-p defect when the sts has a valid pointer with a normal ndf, or a valid conca tenation indicator, in three consecutive frames. n sts pte shall terminate an lop-p defect when it det ects an ais-p defect.
preliminary XRT86SH221 54 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu n sts pte shall detect an ais-p defect when the h1 an d h2 bytes for an sts path contain an all-ones pattern in three consecutive frames. for an stm-nc path, only the h1 and h2 bytes of the first stm-0 need to be observed. n sts pte shall terminate an ais-p defect when the h1 and h2 bytes for the sts path contain a valid sts pointer with a set ndf, or when they contain va lid, identical sts pointers with normal ndfs for three consecutive frames. for an stm-nc path, the c oncatenation indicators must also be valid. n sts pte should terminate an ais-p defect when it de tects an lop-p defect. the rxspoh_proc block chooses n as 8. note that for a pointer to be considered valid, the following tw o conditions from the sdh standard need to be satisfi ed: "a pointer with an in-range value, the n-bits are s et to their normal value." the sdh standard also provides the following recomm endation: "if a pointer processor detects an increment or dec rement operation within three frames after another pointer change operation (e.g. due to transmission errors), it can either ignore that operation or interpret i t as a valid operation. in addition, if the rxspoh_proc is operating in an sdh environment, then the ss bits of the pointer wo rd must be '10'. the above rules can be concisely summarized b y the fsm in table 3 . in table 3 , the label n x event_type denotes an event of event_type occurring in n cons ecutive pointers. the event types are defined in table 3 .
XRT86SH221 preliminary 55 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 f igure 20. p ointer p rocessing fsm t able 3: sdh p ointer e vent t ypes e vent (i ndication ) d escription norm_ptr_ind disabled ndf + ss + offset value equal to active offset ndf_ptr_ind enabled ndf + ss + offset value in range of 0 to 782. ais_ptr_ind h1 = 'hff', h2 = 'hff' inc_ptr_ind disabled ndf + ss+ majority of i bits in verted + no major- ity of d bits inverted + previous ndf_ptr_ind, inc_ ptr_ind, or dec_ptr_ind more than 3 frames ago dec_ptr_ind disabled ndf + ss + majority of d bits i nverted + no majority of i bits inverted + previous ndf_ptr_ind, inc_ptr_ind, or dec_ptr_ind more than 3 frames ago inv_ptr_ind not any of the above new_ptr_ind disabled ndf + ss + offset in range of 0 to 782 but no equal to active offset. inc_ptr_i nd ndf_ptr 3 x norm lop ais 8 x inv_ptr_ind 8 x 3 x 3 x 3 x 3 x ndf_ptr_i 3 x
preliminary XRT86SH221 56 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu b3 processing the rxspoh_proc block calculates the path bip-8 ove r the pertinent bytes of the incoming stream for comparison with the b3 field of the path overhead. the b3 value is calculated according to the followi ng sdh standard rule: n the b3 byte shall carry a bip-8 code, using even pa rity. the sts path bip-8 shall be calculated over a ll bits (783 bytes for an stm-0 spe or nx783 bytes for an stm-nc spe, regardless of any pointer adjustments) of the previous sts spe before scrambl ing and placed in the b3 byte of the current sts spe before scrambling. the rxspoh_proc block outputs an error mask to the rxspoh_stat block after each comparison with b3. payload extraction the rxspoh_stat block determines the positions of t he payload bytes within each frame and generates th e appropriate byte lane enables for the vt mapper int erface. in an stm signal, the fixed columns are defined as the 3 columns following the poh column . the rxspoh _stat block will detect the arrival of the fixed stuff by tes and will not generate any byte lane enables for the vt mapper interface during the fixed stuff bytes. downstream ais insertion the rxspoh_proc block will insert path ais in the d ownstream data when prompted by the rxspoh_stat blo ck. rxspoh_concat block the rxspoh_concat block has an 8 bit internal bus. the concatenated pointer indicator has the value 1001_1111_1111_1111. the sdh standard gives a recom mendation on concatenated pointer processing similar to that of figure 21 . in figure 21 , the following events are defined: conc_ind: ndf enabled + ss1111111111 ais_ptr_ind: 11111111 11111111 inv_ptr_ind: any other. the rxspoh_concat block processes the concatenation pointer indicator for each sts slot according to figure 21 and provides the current concatenated pointer indi cator fsm state of each slot via registers.
XRT86SH221 preliminary 57 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 rxspoh_stat block the rxspoh_stat block captures the status signals f rom the path overhead blocks and stores them in reg isters. the rxspoh_proc block also accumulates rei-p counts from the g1 field and stores them in a 32 bit coun ter. b3 monitor the rxstoh_stat block monitors the b3 error mask fr om the rxspoh_proc block and accumulates the error count in a 16 bit saturation counter. upon software reque st, the count is transferred to a holding register and reset. the software specifies whether to accumulate b3 err or bits or b3 error events where an error event is defined as any non-zero b3 error mask received from the rxs poh_proc block. an interrupt is flagged to notify s oftware whenever a b3 error event occurs. rdi-p monitor there have been two versions of definition for the path rdi defect in the sdh standard. the older vers ion is called single-bit rdi-p (srdi-p) and uses only bit 5 (4th least significant bit) of the g1 byte. the c urrent version is called the enhanced rdi-p (erip-p)and us es bits 5, 6 and 7 of the g1 byte. the erdi-p is de clared when bits 5, 6, and 7 of the g1 byte contain anythi ng other than '011, 000, 001'. the sdh standard has the following standard with respect to receiving the rd i-p signal: n sts pte shall generate an appropriate rdi-p signal, as specified in table 4 , within 100ms of detecting a listed defect. n when sts pte generates a particular type of rdi-p s ignal, it shall generate it for at least 10 frames. n sts pte that does not support erdi-p shall detect a one-bit rdi-p defect when a "1" is received in bit 5 of g1 for 10 consecutive frames n sts pte that supports erdi-p shall detect an rdi-p defect when one of the rdi-p defect codes shown in table 4 (one-bit or enhanced) is received for 5 to 10 cons ecutive frames n sts pte that does not support erdi-p shall terminat e the one-bit rdi-p defect when a "0" is received in bit 5 of g1 for 10 consecutive frames. f igure 21. c oncatenated p ointer i ndicator p rocessing fsm conc lop_c ais_c 8 x inv_ptr_ind 3 x conc_ 3 x 3 x 3 x ais_ptr_ind 3 x conc_ind
preliminary XRT86SH221 58 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu n sts pte that supports erdi-p shall terminate a part icular type of rdi-p defect (one-bit or enhanced) when a code other than the code corresponding to th at defect is received for 5 to 10 consecutive frame s the rxspoh_stat block allows software to specify th e type of rdi-p error to monitor. the software also programs the number of consecutive consistent rdi-p codes that must be observed before it is accepted as valid. when a new valid rdi-p is detected, a flag i s set for software and the rdi-p code that caused t he condition is captured in a register. the rxspoh_sta t block also implements a rdi-p unstable counter. t he rdi- p unstable counter is incremented for each byte tha t differs from the previously received byte. an inv alid rdi-p condition is declared when the rdi-p unstable count er reaches the software specified threshold. the rd i-p unstable counter is cleared to 0 when a valid rdi-p code is accepted. rei-p monitor bits 1 through 4 (most significant 4 bits) of the g 1 byte are allocated to convey the path rei (rei-p) function and are defined in the sdh standard as: n sts pte shall set bits 1 through 4 of the g1 byte t o indicate (to the upstream sts pte) the count of interleaved-bit block errors that it has detected b ased on the sts path bip-8 byte (b3). the error cou nt shall be a binary number from zero to 8. the remain ing seven values shall not be transmitted and shall be interpreted by receiving sts pte as zero errors. the rxspoh_stat accumulates the rei-p counts in a 1 6 bit saturation counter. the count is transferred to a holding register and reset by software request. the rxspoh_stat also flags any non zero rei-l counts. the software can configure the rxstoh_stat block to acc umulate either bit errors or error events. an error event is defined as any non-zero rei-p count. signal label (c2) monitor the c2 byte is allocated to indicate the contents o f the sts spe and is treated as a signal label. the rxspoh_stat block monitors the c2 byte for several conditions according to the sdh standard. n sts pte shall detect an sts payload label mismatch (plm-p) defect within 250ms of the onset of at least five consecutive samples (which may or may no t be consecutive frames) of mismatched sts signal labels (c2 byte), as specified in table 5 . n sts pte should detect a plm-p defect immediately up on receipt of five contiguous frames with mismatched sts signal labels, as specified in table 5 . n sts pte shall terminate a plm-p defect within 250ms of detecting the onset of at least five consecutiv e samples (which may or may not be consecutive frames ) of matched sts signal labels. n sts pte should terminate a plm-p defect immediately upon receipt of five contiguous frames with matched sts signal labels, as specified in table 5 . n sts pte shall terminate a plm-p defect upon detecti ng an uneq-p defect. t able 4: rdi-p s ettings and i nterpretation g1 b its 5, 6 and 7 p riority of erdi-p codes t rigger i nterpretation 0xx not applicable (for srdi-p only, bits 6 and 7 should be '00') no defects no rdi-p defect 1xx not applicable (for srdi-p only, bits 6 and 7 should be '00') ais-p, lop-p one-bit rdi-p defect 001 4 no defects no rdi-p defect 010 3 plm-p, lcd-p erdi-p payload defect 101 2 ais-p, lop-p erdi-p server defect 110 1 uneq-p, tim-p erdi-p connectivity defect
XRT86SH221 preliminary 59 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 n sts pte shall detect an sts path unequipped (uneq-p ) defect within 10ms of the onset of at least 5 consecutive samples (which may or may not be consec utive frames) of unequipped sts signal labels (c2 byte = 00hex) n sts pte should detect an uneq-p defect immediately upon receipt of five contiguous frames with unequipped sts signal labels, as specified in table 5 . n sts pte shall terminate an uneq-p defect within 10m s of the onset of at least five consecutive samples (which may or may not be consecutive frames ) of sts signal labels that are not unequipped. n sts pte should terminate an uneq-p defect immediate ly upon receipt of five contiguous frames with sts signal labels that are not unequipped, as speci fied in table 5 . the rxspoh_stat block allows software to specify th e expected signal label and compares it with the ob served value. if the values mismatch, then a path label mi smatch (plm) error is declared. if the observed val ue is 00hex, then a path unequipped (uneq) error is decla red (and plm cleared). if the observed value matche s the expected value, then plm is cleared. if the obs erved value changes, then a flag is set for softwar e. for a c2 label to be considered valid, it must be receive d in 5 consecutive frames. the rxspoh_stat blocks a lso implements a c2 unstable counter. the c2 unstable c ounter is incremented for each byte that differs fr om the previously received byte. an invalid c2 condition i s declared when the c2 unstable counter reaches 5. the c2 unstable counter is cleared to 0 when 5 consecutive identical c2 bytes are received. the rxspoh_stat b lock implements a mismatch mechanism that can be summari sed in table 6 . t able 5: sts s ignal l abel m ismatch d efect c onditions p rovisioned sts pte f unctionality r eceived p ayload l abel (c2 b yte , in hex format ) d efect any equipped functionality (c2 = anything except h00) unequipped (00) uneq-p any equipped functionality equipped - non specific ( 01) none (matched) equipped - non specific (c2 = h01) a value correspon ding to any payload specific functionality none (mat ched) any payload specific functionality (c2 = anything except h00 or h01) a value corresponding to the same payload specific functional- ity as the provisioned functionality none (matched) any payload specific functionality a value correspon ding to a different payload specific functional- ity as the provisioned functionality plm t able 6: t ruth t able for p ath l abel e rror c onditions e xpected v alue r eceived v alue a ction 00 00 match 00 01 mismatch 00 xx mismatch 01 00 uneq-p 01 01 match 01 xx match xx 00 uneq-p xx 01 match xx xx match xx yy mismatch
preliminary XRT86SH221 60 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu path trace (j1) monitor the j1 byte of the path overhead is used as a path trace identifier. the path trace identifier is moni tored using the following sdh standard rules: n an sdh ne that contains sts pte shall allow the use r to provision, on a per-path basis, the contents o f the sts path trace carried in the j1 byte of the st s path overhead originated by the pte. the transmitted sts path trace string shall be 64 bytes in length. n an sdh ne that contains sts pte shall support a fea ture that allows the contents of the sts path traces to be provisioned as ascii characters. in ad dition, the following apply: n the feature shall allow the user to enter a string of up to 62 characters n the feature shall place no restriction on the conte nt of the string except that the characters shall b e ascii printable characters n the ne shall automatically pad the string entered b y the user to 62 characters using ascii null characters, and then add and characters ( i.e., 'od' and '0a' for a total of 64 characters n each 8 bit ascii character shall be loaded into one j1 byte. n an sdh ne shall support a feature to allow the user to provision the expected ascii-based path trace for each sts path that it terminates and for which tim-p detection has been activated. in addition, th e following apply: 1. the feature shall allow the user to enter a stri ng of up to 62 characters 2. the feature shall place no restriction on the co ntents of the string, except that 3. the characters shall be ascii printable characte rs. n sts pte shall detect a tim-p defect within 30 secon ds (or less) when none of the sampled 64-byte sts path trace strings match the provisioned expect ed value. n sts pte shall terminate a tim-p defect within 30 se conds (or less) when four-fifth (or more) of the sampled sts path trace strings match the provisione d expected value n an sdh ne that is monitoring for changes of the inc oming path trace shall detect when a sustained change in the path trace content occurs. upon detec ting a sustained change, the ne shall send a message to an os. the level of the message shall be not alarmed, and it shall include both the previously received path trace, and the new path tr ace (assuming they are ascii-based). n an sdh ne that is monitoring for a mismatch between the incoming path trace and an expected path trace for diagnostics purposes shall detect when a sustained mismatch occurs. upon detecting a sustained mismatch, the ne shall set an indication for that path and send a message to an os. the leve l of the message shall be not alarmed, and it shall i nclude both the expected path trace, and the new path trace (assuming they are ascii-based). n an sdh that is monitoring the incoming path trace f or diagnostic purposes and that has detected a sustained mismatch shall detect when the incoming p ath trace matches the expected path trace. upon detecting a match, the ne shall clear the indicatio n for that path and send a clear message to the os (if the mismatch was reported to an os). the sdh standard defines the path trace message len gth to be a 16 byte message. the message format is such that the first byte of the message always has a "1" in its most significant bit while the subsequ ent bytes in the message all have a "0" in their most significan t bits. the rxspoh_stat block allows software to specify th e length of the j1 section trace message. this leng th could be 1 or 16 for sdh. the software also specifies whe ther to look for a or a starting "1" bit when the rxspoh_stat block is trying to locate the start of the message. software also specifies the number (3 or 5) of consecutive consistent section trace messages that must be observed before it is accepted. an interrupt is generated when a new section trace message is accepted as valid. the valid section tra ce message is compared with an expected section trace message downloaded to memory by software. a j1 mismatch (j0_mis) flag is raised if the 2 messages are not identical. the rxspoh_stat block also imple ments a j1 unstable counter. the j1 unstable counter is inc remented for each byte that differs from the previo usly
XRT86SH221 preliminary 61 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 received byte. an invalid j1 condition is declared when the j1 unstable counter reaches 8. the j1 unst able counter is cleared to 0 when a valid j0 is accepted . the sdh receive path trace buffers use a 128x8 sing le port memory and a 64x8 single port memory as in the case of the sdh receive section trace buffers. downstream ais insertion control the rxspoh_stat block can be configured to cause do wnstream ais insertion to the cell processor when a ny of the following conditions are detected: ais-p, lop-p , tim-p, j1 unstable, plm-p, uneq-p and c2 unstable . downstream ais insertion to the cell processor is d one by sending all ones in all the extracted payloa d bytes. the software can enable or disable the insertion of path ais to the cell processor on detection of any of the aforementioned conditions. if ais insertion is nece ssary, then an enable signal to the rxspoh_proc blo ck is activated which causes the rxspoh_proc block to ins ert all ones in the payload bytes on the 'rbyte' po rt to the vt mapper cell processor. j1 current expected message buffer 8h00 8h3f j1 current valid message buffer j1 previous received message buffer 8h00 8h3f 8h40 8h7f
preliminary XRT86SH221 62 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rxspoh_cap block the rxspoh_cap block captures the contents of the p ath overhead and stores them for access by the exte rnal processor. the nine path overhead bytes are stored in registers. the rxspoh_cap block issues an interr upt once all the path overhead bytes (9 bytes) for the current frame have been captured. when the last pat h overhead byte of the current frame has been written to its register, an interrupt is raised to notify the software. the contents of the captured path overhead bytes ar e preserved for one frame (i.e., until the next cap ture interrupt) for access by the software. the captured path overhead bytes are serialized and sent as outputs from the chip as shown in figure 22 . rxohframe, rxoh, and rxohvalid are updated on the f alling edge of rxohclk. the rate of rxohclk is programmable in the range from 1.215mhz to 38.88mhz . f igure 22. p ath o verhead i nterface t iming path overhead: clock and signal bits rxohclk rxohframe rxoh j1 j1 j1 j1 j1 j1 j1 j1 b3 b3 3 b3 b3 b3 b3 b3 b3 note: rxpoh_ind is high for poh drop -off the most significant bit is transmitted first rxohclk rxohframe rxoh j1 path overhead: clock and signal bytes b3 rxohvalid c2 g1 f2 h4 rxohvalid
XRT86SH221 preliminary 63 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 stm-0/1 transmit transport processor txstoh_ins block the txstoh_ins block provides a serial port for har dware insertion of the transport overhead bytes. th e hardware inserted sdh oh bytes, if enabled, overrid e the contents of the sdh oh software registers dur ing transmission. the hardware inserted sdh oh bytes ar e forwarded to the txstoh_cont block along with the enable signal. the sdh oh port also has an enable i nput which allows hardware to override the contents of the sdh oh software registers without going through the processor interface. the following picture sho ws the transport overhead j0 byte being enabled. the txohf rame and txohen signals are updated on the falling edge of txohclk while the txohins and txoh signals are sampled on the second rising edge of txohclk following the assertion of txohen. the rate of txohclk is programmable within the rang e from 2.43 mhz to 38.88 mhz. f igure 23. t ransmit t ransport o verhead i nterface t iming transmit sdh overhead: clock and data bits a1 msb a1 lsb txoh a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 j0 j0 j0 j0 j0 j0 j0 j0 txohen note: txpoh_ind is low for sdh oh insertion. the data and enable are latched in on the falling e dge of txohclk at the end of the data period txohclk txpoh_ind txohframe
preliminary XRT86SH221 64 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu hardware rdi-l insertion hardware can enable rdi-l insertion by setting the most significant bit of the b2 byte to "1" on the t toh serial input line. note that software must first enable ha rdware rdi-l insertion. the state of the ttohins pi n has no effect during the b2 slots. txstoh_cont block the txstoh_proc has one 8 bit internal data bus int erface. the txstoh_cont block provides the register file and internal processor interface for the transport sect ion of the sdh transmitter. it selects the value of the transport overhead bytes from either hardware or software acc ording to the control registers and forwards them t o the txstoh_proc block for transmission. the hardware va lue is specified through a parallel data input port . if the transport overhead bytes are serially entered into the chip, it is assumed that a serial to parallel d ata converter has converted the data to parallel format and has p laced the data on the input of the txstoh_cont bloc k at the appropriate instances during transmission. the txst oh_cont also provides control for the transmission of a section trace message (j0 byte). a1/a2 generation the txstoh_cont block generates alternate a1 and a2 values based on hardware or software requests and sends them to the txstoh_proc block via the tx_toh_ data lines. the txstoh_cont block accepts a1/a2 val ues from the hardware input, or alternatively, software can specify an error mask indicating the a1/a2 byt es in which errors should be inserted for diagnostic purp oses. a1/a2 errors are always inserted on frame boundaries, i.e., the a1/a2 error mask is only samp led at the start of every frame. b1 error mask generation the txstoh_cont block allows software to insert err ors into the b1 value calculated and transmitted by the txstoh_proc block. by writing to an appropriate reg ister bit, a software controlled error mask is used to insert errors into the b1 byte. b2 error mask generation the txstoh_cont block allows software to control b2 ber generation through two registers: a byte error mask register and a bit error mask register. the byte er ror mask specifies which of the b2 bytes are to be corrupted and the bit error mask specifies which bits are to be inverted in the b2 bytes that are to be corrupte d. in the case of an 8 bit internal data bus, each bit in the b2 byte error mask corresponds to 4 bytes (i.e., o ne time slot). the b2 byte and bit error masks are sampled before the first b2 byte of each frame if b2 error inserti on is enabled by software. scrambling the txstoh_cont block allows software to disable sc rambling by setting a bit in the control register. otherwise, the sdh data is scrambled using the identical algor ithm as the de-scrambling process. k1/k2 control the k1/k2 bytes contain the aps code. the aps code transmitted either come from software registers or from hardware via the txoh serial pin. note that the 3 l east significant bits of the k2 byte (bits 6, 7 and 8) may be overridden by an rdi-l alarm. rdi-l control (k2 bits 6, 7, and 8) the rdi-l indication bits consist of the 3 least si gnificant bits of the k2 byte. the bits usually con tain portions of the transmitted aps code. however, they are over ridden with the rdi-l pattern 3'b110 if any of the following software configurable conditions occur: los, lof, o r ais-l. rdi-l can also be inserted from hardware v ia the txoh serial pin or forced by software. rdi-l insert ion is done according to the following sdh rules: n te shall generate rdi-l within 125 m s of detecting an ais-l defect (or a lower-layer, t raffic-related, near- end defect). the lte shall generate rdi-l by insert ing the code '110' in bits 6, 7, and 8 of the k2 by te. the lower-layer, traffic-related, near-end defects referred to by r6-200 are los and lof from the rece iver blocks.
XRT86SH221 preliminary 65 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 n if bits 6 through 8 of the k2 byte are not used for other purposes (e.g., the linear aps mode indicati on), the lte shall deactivate rdi-l by inserting the cod e '000' in bits 6, 7, and 8 of the k2 byte within 1 25 m s of terminating the defect that caused it. n if bits 6 through 8 of the k2 byte are used for oth er purposes, the lte shall deactivate rdi-l by inse rting an appropriate code in bits 6, 7, and 8 of the k2 b yte within 125 m s of terminating the defect that caused it to be sent (assuming it has been sent for any mi nimum rdi-l assertion time supported by the ne). n when lte generates rdi-l, it should generate it for at least 20 frames. section trace generation (j0/z0) the txstoh_cont block allows three methods in the t ransmission of the j0/z0 bytes: method 1: the j0 byte is set to all 1 in accordance with the sdh standard rule. unless it is being used for a defined purpose (e.g. , to carry a section trace message once the details of that feature are defined) each j0 and z0 byte shall be s et to a binary number corresponding to its order of appearance in the stm-n frame (i.e., the j0 byte sh all be set to 00000001, the first z0 byte shall be set to 00000010, etc.). method 2: the j1 byte is obtained from the hardware input method 3: the j1 byte is obtained from the message written b y software into the j1 message buffer method 1 is the default unless the software control specifies otherwise. the z0 bytes are always gener ated according to the above rules. the section trace (j0) transmit buffers use a 64x8 single port ram as in the case of the path trace tr ansmit buffers. the memory segments contain the j0 section trace buffers and operate in the same way as the j 1 transmit path trace buffers. rei-l generation (m0/m1) the txstoh_cont block allows three methods in the t ransmission of the m0/m1 bytes: method 1 : the rei-l signal is set according to the b2 error count by the receiver blocks from the most recently received frame method 2 : the rei-l signal is obtained from the hardware inp ut method 3 : the rei-l signal is obtained from software method 1 is the default unless software chooses to enable either method 2 or 3. s1/f1/e1/e2 selection the txstoh_cont block allows either hardware or sof tware insertion of the s1, f1, e1, and e2 bytes. th e default generation method for the s1 byte is reading from t he software registers. the default generation metho d for the e1, f1, and e2 bytes is hardware insertion. the registers contain all zeros upon reset. datacom (d1-d12) selection the data communication bytes are inserted via hardw are only. undefined sdh oh bytes the remaining bytes of the stm-n transport overhead are all currently undefined. the txstoh_cont block inserts all zeros in those bytes in accordance with the sdh standard. n an sdh ne shall have the capability to ignore the v alues contained in all undefined and unused bits an d bytes [except for bip-8 calculations] to prevent mi sinterpretation of the received patterns. n an sdh ne should send an all-zeros pattern (before scrambling) in undefined bits and bytes. all-zero patterns should also be sent in defined bits and by tes if the ne does not support the defined function or if the function has been disabled by the user.
preliminary XRT86SH221 66 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu ais-l control the txstoh_cont provides ais-l insertion capabiliti es according to the sdh standard: n ste shall generate ais-l downstream within 125 m s of detecting an los or lof defect on the incoming signal or the failure of lte supporting provisioned line origination functions. the ais-l shall be generated as an stm-n electrical signal that contai ns valid section overhead and a scrambled all-ones pattern for the remainder of the signal. the txstoh_cont allows software to insert an ais-l condition on the transmitted data by writing to an appropriate bit in the register file. the ais-l con dition is set/unset on frame boundaries. ais-l inse rtion overrides all other frame data insertion schemes wi th the exception of los insertion. los insertion the txstoh_cont block allows software to specify an los condition on the transmitted data which sets a ll data bytes to zero after scrambling. los insertion is en abled by writing a "1" to the appropriate register file bit. los insertion, if specified, overrides all other transm it frame data insertion schemes. txstoh_proc block the txstoh_proc has one 8 bit internal data bus int erface. the txstoh_proc multiplexes transport overh ead data from the txstoh_cont block and spe data from the tx spoh_proc block and inserts them into the data stre am. the txstoh_proc block generates timing and location signals for the other transmitter blocks and perfo rms primitive sdh tasks such as scrambling, b1/b2 calcu lation and insertion, and start of frame (a1/a2) in sertion using control signals from the txstoh_cont block. location strobe generation the txstoh_proc block maintains the location of the current byte (byte lanes) being transmitted and ou tputs time-advanced row, column, and time slot numbers of the data on the byte lane(s) for the other sdh transmitter blocks. the time-advanced location sign als allow for pipeline delays necessary to move the data from the other transmit blocks to the txstoh_proc b lock. a1/a2 insertion during normal operation, the txstoh_proc block inse rts the sdh framing pattern f628 (hex) for the a1 a nd a2 bytes respectively. this can be overridden by non-z ero values from the tx_toh_data input from the txst oh_cont block at the time of insertion. b1 calculation and insertion the txstoh_proc block calculates the bip-8 b1 error code on the scrambled data of the current frame an d inserts it into the b1 byte of the next frame befor e scrambling. errors can be inserted for diagnostic purposes from the tx_toh_data input from the txstoh_proc blo ck. b2 calculation and insertion the txstoh_proc block calculates the bip-8 b2 error code on the unscrambled data of the current frame except for the section overhead bytes and inserts it into the b2 bytes of the next frame before scrambling. e rrors can be inserted for diagnostic purposes from the tx_toh _data input from the txstoh_proc block. two memories are used in the b2 error code calculat ions for the txstoh_proc block. one memory is used to store the running value of the b2 error calculation s. this memory is a 12x8 dual port ram with one por t for reads and one port for writes. this is necessary be cause as the hardware is calculating the b2 code fo r each sts, it needs to store the new value into the memor y and at the same time fetch the current code for t he next sts from memory. the second memory is a single port 12x8 ram used to store the final b2 codes for all the sts's. this memory is read at the b2 byte locations for comparisons and written into in the a1 byte lo cations to store the final b2 codes for the previous frame. fo r the 8 bit version of the rxstoh_proc block, the b 2 ram widths are 8 bits.
XRT86SH221 preliminary 67 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 scrambling the txstoh_proc block scrambles all the bytes of th e sdh frame except for the a1, a2, and j0/z0 bytes. scrambling may be disabled by software. scrambling is controlled on frame boundaries. that is, the txstoh_proc block will sample the scram_enable inpu t at the beginning of each frame and scrambling is performed on the entire frame if the scram_enable i s "high". sdh oh data insertion for the rest of the sdh oh bytes, the txstoh_proc s imply takes the data on the txoh input at the time of transmission, and inserts it into the corresponding location in the sdh frame. the sdh oh bytes intend ed to be inserted in this manner are: m0/m1, j0, s1, k1, k2, f1, e1, e2, the data communication bytes (d1-d1 2) and the undefined and growth bytes. spe data insertion the txspoh_proc block places spe data on the tx_pat h_data input of the txstoh_proc according to the lo cation signals generated by the txstoh_proc block. the txs toh_proc takes the spe data and inserts it into the transmit sdh frame at the appropriate instances in time. ais-l/los insertion the txstoh_proc can apply either an ais-l or a los condition as described in previous sections accordi ng to control signals from the txstoh_cont block.
preliminary XRT86SH221 68 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 4.9 telecom bus interface the device's telecom bus interface supports the fol lowing features: option to enable/disable parity generation. option to select if parity is generated over data o nly or data and pl and c1j1 and alarm signals. option to select if odd or even parity is used. accepts 8 khz transmit frame pulse and complementar y transmit reference clock to synchronize transmit data. 4.9.1 transmit telecom bus the tansmit telecom bus interface consists of the f ollowing outputs: 8-bit data bus txd_d[7:0], clock txd_clk, payload indication txd_pl, timing indicati on txd_c1j1v1_fp, parity txd_dp, and a alarm indication txd_alarm. the device also allows a comm on set of reference timing signals for synchronizin g the data input to each of the telecom bus ports for the cases where transmit re-phase is not available on the other side. the telecom bus port operates at 19.44 mhz on stm-1 and 6.28 mhz on stm-0. the subsections below summarize the functionality o f the telecom bus interface signals. tx51_19mhz is provided as a reference clock to put data out onto the telecom bus ports. these signals are 19.44/6.28 mhz. this clock must be used to source the data to be tr ansmitted on the appropriate telecom bus. an 8khz pulse ( txsbfp_in_out ) is input on the falling edge of tx51_19mhz once e very frame period and is one tx51_19mhz clock cycle wide. it is used to sync hronize the data arriving at the txd_d[7:0] outputs . a 16- bit latency counter can be configured to determine the latency between the frame pulse and the associa ted input data (c1). figure 24 shows the relationship between the input telecom b us data and the txsbfp_in_out signal. the transmit telecom bus clock output (txd_clk) is used to clock the transmit telecom bus output signa ls. it must be synchronous with the tx51_19mhz clock. also , no phase relationship is required between tx51_19mhz and the txd_clk. the txd_d[7:0] stream m ust contain valid pointer bytes and the poh. the telecom bus also generates the value of the tra nsmit telecom bus parity output (txd_dp). the parit y calculations can be configured through the use of t he control bits in the interface control registers. the f igure 24. t ransmit t elecom b us i nterface t iming c1 pulse txa_c1j1 txa_pl txa_d[7:0] txa_ck (inverted) txa_ck a1 a1 txrefclk txsbfp c1 pulse a1 a2 latency n = 5 a2 a2 c1 j1 pulse c1 c1 j1
XRT86SH221 preliminary 69 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 transmit telecom bus alarm output (txa_alarm) is ge nerated to tell the external device to generate ais -p in the stm-0/stm-1 for which the alarm occurs. 4.9.2 2khz mode in stm-1 to align the v1 bytes with h4 in stm-1, the part mu st be configured for 2khz. with a 2khz frame pulse applied to each of the voyager lite devices, the parts can align vt superframe boundaries. this will allow v1 bytes within each device to match one another. the txd_c1 j1v1_fp will pulse "high" for all c1j1 bytes. howev er, it will only pulse "high" during the v1 byte. v2, v 3, and v4 will not be indicated by the external fra me pulse. 4.9.3 receive telecom bus the receive telecom bus interface consists of the f ollowing inputs: 8-bit data bus rxd_d[7:0], clock (rxd_clk), spe indication (rxd_pl), c1j1 indication (rxd_c1j1v1_fp), parity (rxd_dp), and a alarm indication (rxd_alarm). all of the receive telecom bus ports operate at 19.44/6.28 mhz. the subsections below summarize the functionality o f the receive telecom bus interface signals. the re ceive telecom bus clock input rxd_clk is used to clock in the receive telecom bus input signals from an exte rnal device. the clock edge on which the telecom bus sig nals are clocked is programmable via the ckinv cont rol bits. figure 26 shows the functional relationship of the receive t elecom bus signals. each receive telecom bus port has an 8-bit wide dat a bus that inputs the stm-0/stm-1 data from an exte rnal device. the receive telecom bus data is byte-align ed and the entire payload, including sdh oh and poh , is passed in the device. the receive telecom bus c1j1 input (rxd_c1j1v1_fp) can be provisioned to provide two different types of indications, depending on th e register setting. when cpos is set to "1", the corresponding rxd_c1j1v1_fp signal provides two pul ses. for all sub-frames, the receive telecom bus pl inpu t (rxd_pl) is "low" during the sdh oh bytes in the rxd_d[7:0] stream and is "high" during the spe byte s. this includes cases where pointer adjustments ar e performed and the spe needs to be adjusted about th e h3 bytes. for example, the h3 bytes are payload b ytes during the frame in which a pointer decrement occur s, therefore the rxd_pl signal will be "high" coinc ident with the h3 bytes for that frame. also in the frame where a pointer increment occurs, the three bytes after the h3 bytes become stuff, therefore the rxd_pl signal will be "low" for those bytes. the parity checking can be configured through the use of the control bits in t he interface control registers. f igure 25. c1j1v1 p ulse in stm-1 2 k h z m ode f igure 26. r eceive t elecom b us i nterface t iming 2khz fp c1 j1 c1 j1 c1 j1 c1 j1 v1 c1 j1 v1 txd_c1j1v1_fp
preliminary XRT86SH221 70 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu the receive telecom bus alarm output (rxd_alarm) is generated by an external device in response to an alarm condition that will cause ais-p to be generat ed. the rxd_alarm input will remain active for the duration of the alarm condition that causes it to b ecome set.
XRT86SH221 preliminary 71 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 4.10 vt mapper interfaces and protocols this block has three interfaces to the outside worl d: the internal bus interface through which the block communicates wit h the m p interface block which interfaces to the external processor that controls and monitor s the vt mapper. the mid bus interface through which the block communicates wit h the blocks processing the higher levels of sdh overhead. the e1 i/o interface up to 21 digital signals. internal bus interface figure 27 shows the internal synchronous bus structure. it c onsists of two 8-bit data buses, an 8-bit address bus, and 5 control lines: clock (clk), select (sel) , read (read), data transfer acknowledge (dtack), a nd interrupt request (irq). all of these lines are active high. byte-oriented addressing is used for all of the add ress maps. f igure 27. i nternal b us s tructure ( master) read rdata [7:0] wdata [7:0] addr [7:0] sel dtack slave block 0 slave block 1 or micro- processor bus address decoder hi low ... irq or
preliminary XRT86SH221 72 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu internal bus signals signals and their usage are described. clk , sel and read are driven high or low by the pif block, based on the clk , chip select , and we signals from the microprocessor. irq and dtack are low or high driven by internal registers. addr, rdata and wdata may be undefined a s long as no read or write action is taken. all sig nals are clk aligned and sensitive to the positive edge of c lk. s ignal d irection d escription clk input system clock signal, input from external pr ocessor sel input select signal, when it goes high, selects i nternal register read input read/write control signalhigh: read data f rom data bus.low: write data to data bus. dtack output data transfer acknowledge signal, comes from internal registers, indicate internal regis- ters are ready to send or accept data. addr[7:0] input register address. irq output interrupt request signal when it goes to 1 indicates an interrupt request. rdata[7:0] output reads data signals from internal re gister. wdata[7:0] input write data signals to internal regis ter.
XRT86SH221 preliminary 73 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 mid bus interface the interface between the vtm and the other sdh blo cks is a single edge synchronous interface. it cons ists of a clock, enable pair, and an 8-bit data bus in each direction. the enable signals are active high and data is transferred on the rising edge of the corresponding clock. sdh to vtm direction in this direction, the higher level sdh block is se nding data to the vt mapper. data presented on the rxbyte[7:0] data bus of the vtm by the sdh block mu st be valid to be sampled on the rising edge of rxc lk when rxbyte_en is "high". the vtm block samples the rxby te_en and rxbyte[7:0] lines on each rising edge of rxclk. if rxbyte_en is "high", the data on rxbyte[7:0] is pro cessed as valid data. the transitions on the rxbyte [7:0] and rxbyte_en lines should be timed to satisfy the vtm' s setup & hold requirements with respect to rxclk. for all timing diagrams in this section, it is impl ied that the data lines can change at every clock c ycle. only when the nature of the data carried on the data lin es changes is there a boundary shown on the data li ne. the start of superframe signal is asserted while th e first v1 byte of the superframe is present on rxb yte. f igure 28. m id b us i nterface f igure 29. sdh to vtm data transfer with zero pointer offset s d h b l o c k s v t m t x c l k t x b y t e _ e n r x c l k r x b y t e _ e n r x b y t e [ 7 : 0 ] t x b y t e [ 7 : 0 ] r x s o s t x s o s toh bytes + poh byte rxclk payload bytes rxbyte rxbyte_en toh bytes + poh byte rxsos v1
preliminary XRT86SH221 74 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu vtm to sdh direction when the sdh block is receiving data from the vtm, txbyte_en is used as a command signal. when the sdh block asserts txbyte_en "high", data from the vtm i s produced on the next rising txclk edge. figure 30 gives an example of such a transaction. transitions of li nes txbyte[7:0] and txsos occur on the rising edge of txclk so setup time requirements of up to one txclk period c an be satisfied. it is up to the interface designer to make sure that the other timing requirements of circuits connected to the vtm are satisfied. although a minimum of buffering is done at the vtm mid bus output to compensate for the jitter introdu ced by the transport and path overhead columns (sdh oh & p oh), it is assumed and required that txbyte_en and txclk clock ticks will occur at an average frequenc y of 6.192mhz (i.e. 6.48mhz txclk with a 86:90 enab le ratio) and will be approximately equally spaced (burst rea ds are not supported). e1 i/o line interface each of the 21 e1 input channels has its own clock and data input signals (internally provided from th e e1 line interface). in addition, each of the 21 e1 input ch annels has a start of superframe input that is used for synchronous mappings of e1 signals. each of the 21 e1 output channels has it's own clock, data and sta rt of superframe output signals (internally routed to the e1 line interface). input data and start of superf rame are sampled on the rising edge of the input clock. outp ut data and start of superframe are valid to be sam pled on the rising edge of the output clock. when doing synchronous mappings of e1 signals, the position of the first bit of an e1 superframe is in dicated by a high on the start of superframe line. f igure 30. vtm to sdh data transfer txclk txbyte txbyte_en txsos v1 valid bytes from vtm
XRT86SH221 preliminary 75 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 f igure 31. e1 i nterface t iming (i nternal to the c hip ) f igure 32. e1 i nterface t iming (e1 synchronous mapping , i nternal to the c hip ) clk addr sel rbenab read wdata dtack x valid x x x valid clk addr sel rbenab read wdata dtack x valid x x x valid
preliminary XRT86SH221 76 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu design description the function of this reusable block is limited to t he construction and extraction of the vt structured content of the sdh stm-0 payload capacity / sdh vc-3 as descri bed by telcordia's gr-253-core generic requirements and itu-t's g.707 recommendations. th e rest of the work for the higher levels of hierarc hy including transport and path overhead is handled by the stm-0 sdh blocks. vt structured stm-0 payload capacity this section briefly describes the structure of the sdh data stream used to carry lower bit-rate chann els. the stm-0 payload capacity is made up of 84 columns of 9 rows each. the payload capacity is divided equall y amongst seven groups. each group can contain three vt2/tu-12 tributaries. vt2/tu-12 tributaries are us ed to carry an e1 signal. vt superframe four consecutive stm-0 frames of payload capacity a re used to make up a vt superframe. the first byte of each tributary in each frame has a special function . these special bytes are called v1 to v4. v1 & v2 : vt payload pointer the v1 and v2 bytes form the vt payload pointer. in asynchronous mappings or on transmission, the vt payload pointer is assigned a fixed value by this b lock such that the v5, j2, z6/n2 and z7/k4 bytes immediately follow the v1 to v4 bytes. in synchrono us mappings or on reception, the vt payload pointer is processed as prescribed in telcordia and itu. each time a received vt payload pointer is incremented o r decremented, internal counters are available to be read by the processor in registers bip2cnt1 to bip2cnt21 and reicnt1 to reicnt21 are incremented. v3 : vt pointer action byte this byte is used as a negative stuff byte when req uired by a pointer decrement. otherwise, it is unde fined. it is never used by this block on transmission of asyn chronously mapped signals. in synchronous mappings or on reception, this byte is processed along with the vt payload pointer bytes as prescribed in the telc ordia and itu documents. v4 : undefined this byte is reserved for future growth and is trea ted as undefined. it is ignored on reception and is transmitted as all zeros. vt path overhead each virtual tributary has it's own set of path ove rhead bytes which are processed as described in the following paragraphs. v5 : vt path error checking, signal label and path status the bit assignments for the v5 byte are shown in table 7 . bits [7:6] of v5 are used for error performance mon itoring. a bip-2 scheme is defined as follows. when generating a tributary, bit 7 is set to the exclusi ve-or of all the odd numbered bits (bits 7,5,3 and 1) of the previous vt spe (including the v5, j2, z6/n2 or z7/ k4 byte but not the v1 to v4 bytes, except v3 when it is used as a negative stuff byte), bit 6 is set to the exclusive-or of all the even numbered bits (bits 6 , 4, 2 and 0) of the previous vt spe. when terminating a tributary, bit 7 is compared to the exclusive-or of all the od d numbered bits of the previous vt spe, bit 6 is comp ared to the exclusive-or of all the even numbered b its of the previous vt spe. if there is any difference, bi t 5 of v5 (rei-v) of the peer tributary generator i s set to "1", t able 7: v5 - vt p ath e rror c hecking , s ignal l abel and p ath s tatus 7 (msb) 6 5 4 3 2 1 0 (lsb) bip-2 rei-v rfi-v signal label rdi-v
XRT86SH221 preliminary 77 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 otherwise it is set to "0". detected errors are tal lied in the bip2cntx counters that can be read by t he processor in registers bip2cnt1 to bip2cnt21 bit 4 of v5 is used for vt path remote failure indi cation (rfi-v). as described in gr-253-core, when automatic rfi-v insertion is enabled by writing "1" to bit vtrfien of registers ins1 to ins21, rfi-v w ill be signalled by inserting a "1" in the rfi-v bit of by te v5 when lop-v, ais-v, uneq-v or plm-v is detecte d for more than 2?? seconds on the received tributary in the corresponding time slot. the rfi-v signalling is removed, and bit rfi-v of byte v5 is cleared if the condition that triggered it is absent for 10? sec onds. bits [3:1] of v5 are used for vt path signal label and indicate the contents of the tributary. only th e following codes are generated by the tributary generator or e xpected by the vt pte: 000 : unequipped or not provisioned 010 : asynchronous mapping of e1 100 : byte synchronous mapping e1 bit 0 of v5 is used for one-bit vt path remote defe ct indication (rdi-v) as described in gr-253-core. when automatic rdi-v insertion is enabled by writin g "1" to bit vtrdien of registers ins1 to ins21, rd i-v will be signalled by inserting a "1" in the rdi-v bit of byte v5 when lop-v, ais-v, uneq-v or plm-v is dete cted on the received tributary in the corresponding time slot. vc-12 path remote loopback signaling voyager-lite supports in-band signaling within the low-order vc-12 path overhead to request vc-12 path remote loopback (e1 payloads) provisioning at down- stream equipment. signaling will be sent on the st m-1 transmit output from the request originating system (sending system) and received on the stm-1 input o f the far-end system (receiving system). once the receiv ing system detects this in-band message, a status f lag is set to indicate the remote loopback request detecti on. the system software will detect this flag thro ugh interrupts and subsequently provision the appropria te low-order path for remote loopback. the sending system shall continue sending the in-band message u ntil such time that the remote loopback should be removed. at this time, the vc-12 path overhead/payl oad content within the stm-1 transmit output of the sending system shall resume normal function. upon detecting termination of the remote loopback reques t, the receiving equipment shall set a status flag to indi cate the clearance of the remote loopback request. the system software can detect this flag and subsequent ly remove the remote loopback provisioning for the appropriate low-order path. this function is provid ed on a per vc-12 basis. the lsb of the bit stuff byte immediately following v5 is used as the location for the remote loopback request messaging. during normal operation, this bit will contain the usual stuff bits. however, during remo te loopback request transmission, this bit shall transmit a con tinuous, alternating pattern of 1s and 0s. the pa ttern shall always begin with a "1" and terminate immediately u pon release of the software control bit for the rem ote loopback request enable. the receiving equipment sh all monitor this bit location for the pattern of "1010101010", or exactly ten bits of alternating 1' s and 0's with the first bit having a value of "1". once the stated pattern is detected, the receiver sets a sta tus flag indicating detection of the remote loopbac k request. this bit should be reset upon read and should not b e set again until clearance of the remote loopback request is detected, and a new remote loopback request mess age is received. detection and cancellation examples: j2 : vt path trace byte j2 is used to transmit repetitively a low orde r path access point identifier so that a path recei ving terminal can verify its continued connection to the intended transmitter. the path access point identi fier supports both 16-byte and 64-byte frame as the j0 b yte defined in the earlier section. the 64 byte ram is used on a shared basis with j2 a nd n2 bytes. when the 64 byte j2 message mode is configured, the n2 tandem connection feature is di sabled. when the j2 message mode is configured as 1 6 byte, two 16 byte segments are used for tc (tandem connection) and j2.
preliminary XRT86SH221 78 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu z6/n2 : vt path growth (tandem connection, tc) n2 is allocated for tandem connection monitoring fo r the vc2, vc-12 and vc-11 level. the structure of the n2 byte is given in table 8 . bits 1-2 are used as an even bip-2 for the tandem c onnection. bit 3 is fixed to "1". this guarantees that the con tents of n2 are not all zeroes at the tc source. th is enables the detection of an unequipped or supervisory unequ ipped signal at the tandem connection sink without the need for monitoring further oh-bytes. bit 4 operates as an "incoming ais" indicator. bit 5 operates as the tc-rei of the tandem connecti on to indicate errored blocks caused within the tan dem connection. bit 6 operates as the oei to indicate errored block s of the egressing vc-n. bits 7-8 operate in a 76 multiframe as: n the access point identifier of the tandem connectio n (tc-apid); it complies with the generic 16-byte string format of j0; n the tc-rdi, indicates to the far end that defects h ave been detected within the tandem connection at the near end tandem connection sink; an 8-bit ount er is provided for counting the number of rei bits received as 1 in bit 5 of n2. an rei indicates that the distant end has detected one or two errors between the bip-2 calculation of the previous frame (all the bytes) and the bip-2 value carried in the n2 byte in the current frame. n the odi, indicates to the far end that tu-ais has b een inserted at the tc-sink into the egressing tu-n due to defects before or within the tandem connecti on; an 8-bit counter is provided for counting the number of oei bits received as equal to 1 in bit 6 of n2. an oei indication (a1) indicates that the di stant end has detected one or two errors when, the bip-2 calculated for the previous frame is compared against the bip-2 value carried in the v5 byte in t he current frame. n reserved capacity (for future standardization). n the structure of the multiframe is given in table 9 and table 10 . tcm functionality - source if no valid tu-n is entering the tandem connection at the tc-source, a valid pointer is inserted. this results in a vc-ais signal and bit 4 is set to "1". even bi p-2 parity is calculated over the inserted vc-ais s ignal and written into bits 1-2 of n2. if a valid tu-n is entering the tandem connection a t the tc source, then even bip-2 parity is calculat ed over the incoming valid vc-n or the inserted vc-ais sign al and written into bits 1-2 of n2. n the bits tc-rei, tc-rdi, oei, odi are set to "1" if the corresponding anomaly or defect is detected at the associated tc-sink of the reverse direction. n the original bip-2 is compensated according to the algorithm described below. n ote : in an unequipped or supervisory unequipped signal e ntering a tandem connection, the n2 and v5 bytes ar e overwritten with values not equal to all zeroes. t able 8: n2 byte structure b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 bip-2 "1" "incoming ais" tc-rei oei tc-apid, tc-rdi odi, reserved
XRT86SH221 preliminary 79 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 tcm functionality - sink if no valid tu-n is present at the tc-sink, a defec t caused within the tandem connection is stated and the tc- rdi and odi conditions apply. if a valid tu-n is present at the tc-sink, the n2 b yte is monitored: an "all-zeroes" n1-byte indicates a miss or discon nection within the tandem connection. in this case, the tc-rdi and odi-bits are set to "1" in the reverse d irection and tu-ais is inserted in the egressing tu -n. bit 4 of the received n2 is set to "1" to indicate that a defect has already occurred before the tande m connection. in this case, the odi bit is set to "1" in the reverse direction and tu-ais is inserted in the egressing tu-n. the multiframe in bits 7 and 8 is recovered and the contents are interpreted. if the multiframe cannot be found, the tc-rdi and odi bits are set to "1" in th e reverse direction and tu-ais is inserted in the e gressing tu-n. the tc-apid is recovered and compared with the expe cted tc-apid. in the case of a mismatch, the tc-rdi and odi bits are set to "1" in the reverse directio n and tu-ais is inserted in the egressing tu-n. the even bip-2 is computed for each bit pair of eve ry byte of the preceding vc-n including v5 and comp ared with the bip-2 retrieved from the v5 byte. a differ ence not equal to zero indicates that the vc-n has been corrupted and, then the oei bit is set to "1" in th e reverse direction. furthermore the actual bip-2 i s compared t able 9: b 7- b 8 multiframe structure f rame # b 7- b 8 definition 1-8 frame alignment signal: 1111 1111 1111 1110 9-12 tc-apid byte #1 [ 1 c1c2c3c4c5c6c7] 13-16 tc-apid byte #2 [ 0 x x x x x x x ] 17-20 tc-apid byte #3 [ 0 x x x x x x x ] : : : : : : 65-68 tc-apid byte #15 [ 0 x x x x x x x ] 69-72 tc-apid byte #16 [ 0 x x x x x x x ] 73-76 tc-rdi, odi and reserved t able 10: s tructure of frames # 73 - 76 of the b 7- b 8 multiframe tc-rdi, odi and reserved capacity f rame # b 7 definition b 8 definition 73 reserved (default = "0") tc-rdi 74 odi reserved (default = "0") 75 reserved (default = "0") reserved (default = "0") 76 reserved (default = "0") reserved (default = "0")
preliminary XRT86SH221 80 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu with the bip-2 retrieved from the n2-byte. a differ ence not equal to zero indicates that the vc-n has been corrupted within the tandem connection and, then th e tc-rei is set to "1" in the reverse direction. if tu-ais is not inserted at the tandem connection sink, then the n2-byte is set to all zeroes and the bip is compensated according to the algorithm described be low. multiframe generation and synchronization loss of multiframe occurs when two consecutive fram e alignment signals (1111 1111 1111 1110) are detec ted in error (i.e., one or more errors in each fas). mu ltiframe alignment is recovered when one consecutiv e non- errored fas are found. two status bits are used to indicate the loss of multiframe (txanlomf, rxdnlomf). the tc trace identifier message comparison is based on the same state machine as that used for the 16- byte j2 message. the tc lock is removed (instable, inv) when 3 messages are received in error and the tc_in v alarm is declared. the tc lock is established when 3 valid, identical messages are received. a compari son is performed between the microprocessor-written tc and the contents of the incoming message. the message consists of tc trace id bytes 0 to 15. a tc trace i dentifier mismatch (tc_mis) alarm is declared when any byte does not match. recovery occurs when there is a match between the expected message and the accepted message. bit 8 in frame 73 is defined as a tandem connection remote defect indication (tc rdi). a tc rdi alarm occurs when a "1" has been detected in bit 8 in fra me 73 for five consecutive multiframes (where each multiframe is 38 ms). the tc rdi alarm state is exi ted when bit 8 is equal to 0 for five consecutive m ultiframes. an alarm indication is reported as tc_rdi. bit 7 in frame 74 is defined as a tandem connection outgoing defect indication (tc odi). a tc odi alar m occurs when a "1" has been detected in bit 7 in fra me 74 for five consecutive multiframes (where each multiframe is 38 ms). the tc odi alarm state is exi ted when bit 7 is equal to 0 for five consecutive m ultiframes. an alarm indication is reported as tc_odi. tandem connection unequipped status unequipped tandem connection detection is provided. five or more consecutive received tandem connectio n n2 bytes equal to xx00 0000 result in a tc unequipp ed indication (tc_uneq). the alarm state is exited when five or more consecutive received tandem connection n2 (z6) bytes are not equal to xx00 0000. note tha t bits 1 and 2 of the n2 (z6) byte are masked (shown as x) and do not affect the detection. the xx represents a don't care value and may be equal to a bip-2 value. bip-2 compensation since the bip-2 parity check is taken over the vc-n (including n2), writing into n2 at the tc-source o r tc-sink will affect the vc-2/vc-12/vc-11 path parity calcul ation. unless this is compensated, the error monito ring mechanism of bip-2 is corrupted. because the parity should always be consistent with the current state of the vc-n, the bip has to be compensated each time the n 2-byte is modified. since the bip-2 value in a give n frame reflects the parity check over the previous f rame, the changes made to bip-2 bits in the previou s frame shall also be considered in the compensation of bip -2 in the current frame.
XRT86SH221 preliminary 81 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 z7/k4 : vt path aps and vt path remote defect indic ation bits [7:4] are used for vt path aps signalling (aps -v). bits [3:1] are for the optional enhanced vt path re mote defect indication (erdi-v). bits 5 to 7 of byt e k4 may provide a remote defect indication with additional differentiation between the remote payload defect ( lcd), server defects (ais, lop), and the remote connectiv ity defects (tim, uneq). the optional codes from table 11 will be used. use of the "010" code to indicate pa yload defects does not imply a requirement to use the "101" and "110" codes to distinguish between se rver and connectivity defects. n otes : 1. lcd is the only currently defined payload defect and is applicable to atm equipment only. 2. old equipment may include lcd or plm as a trigger condition. plm and uneq have previously been cover ed by slm. 3. remote server defect and server signal failure ar e defined in recommendation g.783. for these optional codes, bit 7 is always set to th e inverse of bit 6 to allow equipment which support s this feature to identify that it is interworking with eq uipment that uses the single bit rdi. in such a cas e, equipment at both ends will interpret only v5. bit 0 is reserved for future growth and is treated as undefined. t able 11: k4 ( b 5- b 7) coding and interpretation b 5/ b 8 of v5 b 6 b 7 m eaning t riggers 0 0 0 no remote defect no remote defect 0 0 1 no remote defect no remote defect 0 1 1 no remote defect no remote defect 0 1 0 remotepayload defect lcd(note 1) 1 0 0 remote defect ais, loptim, uneq(or plm, lcd)(note 2) 1 1 1 remote defect ais, loptim, uneq(or plm, lcd)(note 2) 1 0 1 remoteserver defect ais, lop(note 3) 1 1 0 remoteconnectivity defect tim,uneq t able 12: z7/k4 - vt p ath g rowth and vt p ath r emote d efect i ndication 7 (msb) 6 5 4 3 2 1 0 (lsb) aps-v erdi-v undefined
preliminary XRT86SH221 82 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu make payload block (mkp) figure 33 and figure 34 show the internal workings of the make payload blo ck. f igure 33. mkp (m ake p ayload ), one of seven mkg : m ake vt/tu g roup 3 :1 mkt : make tributary loopback not equipped e1 #1 e1 #21 . . . e1 #2 test pattern test channel loopback not equipped e1 #1 e1 #21 . . . e1 #2 test pattern ... . . . byte interleaving vt #2 vt #3 ... vt/tu group output mkt : make tributary 3 x 32 :1 3 x 32 :1 clk data clk data test channel sof sof
XRT86SH221 preliminary 83 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 f igure 34. mkp (m ake p ayload ), vt/tu g roup i nterleaving . 7 :1 vt/tu group 1 vt/tu group 3 vt/tu group 4 vt/tu group 5 vt/tu group 7 vt/tu group 6 vt/tu group 2 mid bus txbyte[7 :0] txclk txbyte_en
preliminary XRT86SH221 84 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu make tributary block (mkt) each of the 21 make tributary blocks (mkt) illustra ted in figure 35 takes the output of its channel multiplexer and builds a tributary suitable for byte interleavi ng into a tributary group. it takes care of deseria lization, vt poh generation and stuff bit control. if the alarm indication signal (ais) is asserted, a tributary ma de up of all ones is generated. f igure 35. m ake t ributary (mkt) mkt : make tributary clock data fifo data read empty low high reset c1 c2 deserialise 19.44mhz txclk data read vt poh ais tsize_sel rdi rei rfi clock domain boundaries sos start of superframe
XRT86SH221 preliminary 85 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 extract payload block (xtp) this block, illustrated in figure 36 , extracts the individual e1 channels from the sdh data stream. the seven groups are first de-interleaved, fixed stuff column s are removed, and then one to four tributaries are extracted from each group. this block handles the v1-v2 vt pa yload pointer processing, vt poh, and stuff bits. test channel two extra e1 channels (one input, the other output) are available to be used as a test channel. the te st channel's input and output can be used in the same way as any of the 21 e1 signals' inputs and outputs . they can be mapped into or extracted from the sdh stream , they can be looped back, or fed by or compared to the test pattern generator. test pattern generator (tpg) the test pattern generator can generate or compare to a pseudo random test pattern of length 2 15 -1, a fixed pattern of all zeros, all ones, or alternating ones and zeros as recommended in itu/ccitt recommendati on o.151. the pseudo random pattern is generated by a fifteen stage shift register whose 14th and 15th st age outputs are added in a modulo-two stage, and the re sult is fed back to the input of the first stage. t he fed back bit is inverted before it is used as the next bit i n the pseudo random sequence either for output or t o be compared to. the test patterns of correct bit rate is made available to each of the seven groups accor ding to the size of the tributaries assigned to each group. in addition to valid clock and data signals, the t pg generates a valid start of superframe pulse one e1 clock tick wide at appropriate intervals, for synch ronous e1 mappings. this will emulate four null signalling bi ts. f igure 36. e xtract p ayload (xtp) xtp : extract payload de- interleave . . . xtg : extract group 1 xtg : extract group 7 1 21 30 x 3 x 32 : 1 mid bus from sdh e1 data, sos & clock outputs . . . loopback test channel test pattern unequipped start of superframe rxclk rxbyte_en clock domain boundaries
preliminary XRT86SH221 86 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu reference clocks generation (rcg) the reference clock generator block (rcg) divides t he 19.44mhz input clock to generate clock signals o f precise frequencies and signals used in loopback mo des. the sdh loopback clock lbclk is simply a 6.48m hz clock obtained by dividing the input frequency by t hree. the loopback byte enable signal lbbyte_en is asserted for 86 out of every 90 lbclk clock ticks. the loopb ack start of superframe signal lbsos is a single pu lse, one lbclk tick wide that occurs once every 4x9x90 lbclk ticks. f igure 37. r eference c locks g enerator (rcg) 1 : (4x9x90) C 1 lbsos 19.44mhz ? 9 / ? 10 add 63 mod 128 2.048mhz ? 3 / ? 4 add 21 mod 263 6.312mhz 86 : 4 ? 3 lbclk lbbyte_en
XRT86SH221 preliminary 87 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 data interface between sdh/framer and mapper the data interface between the sdh and the mapper b locks consist of three lines/buses in each directio n: clk, byte lane, and byte enable. there are 1 byte lanes (8 bits) and 1 byte enable running at a data rate o f 6.48mhz. in the receive direction, the sdh payload data is s ent to the receive mapper block. data is presented on the byte lane on the rising edge of rclk with rbyte_en "high" representing the data is valid. the mapper b lock then fetches the data on the next rising edge of rclk. in the transmit direction, the sdh payload data is pulled from the transmit mapper block. tbyte_en is used as an acknowledge signal indicating that data is recog nized. when tbyte_en is asserted "high", data from the mapper is latched into the sdh block on the next ri sing tclk edge. f igure 38. r eceive sdh/f ramer -atm i nterface f igure 39. t ransmit sdh/f ramer m apper i nterface x rclk valid data rbyte _en rbyte_en x x tclk valid data tbyte _en tbyte_en x
preliminary XRT86SH221 88 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu e1 frame synchronization the e1 framer establishes frame and multiframe boun daries by searching for frame alignment, crc multiframe alignment, and channel associated signal ing multiframe alignment in the incoming pcm data stream, and provides an output clock useful for dat a conditioning and decoding. user access to the e1 framer is via the microprocessor bus interface. the framer incorporates a robust framing algorithm which prev ents false synchronization on patterns that mimic the fr aming bits. the e1 framer monitors the incoming data stream fro m the liu line interface module for loss of frame, loss of crc multiframe and cas multiframe alignment based o n user-selectable criteria, and searches for new fr ame alignment pattern when sync loss is detected. when sync loss is detected, the framer begins an off-li ne search for the new alignment and shifts into resync mode; all output timing signals remain at the old alignme nt during this period. when one and only one candidate is qu alified, the output timing will move to the new ali gnment at the beginning of the next frame (or multiframe). o ne frame later, the framer resumes the normal sync monitoring mode and outputs the valid sync signal. the general synchronization flow diagram is illustr ated in figure 40 . fas synchronization three steps are involved in the synchronization pro cess. the first one is finding fas frame alignment . the second one searches for fas using one of two user s electable algorithms as defined in recommendation g.706. in addition, a two frame check sequence can be added optionally to either one of these two algo rithm to provide protection against false frame alignment in the presence of random mimic patterns. f igure 40. e1 f ramer s ynchronization f low d iagram state is "resync" ? lof ? initial enter "resync" state frame alignment search frame lock & enter "monitor" state enter "monitor" state of-line search & switch state in-sync ? shadow synchronization no yes no yes no yes
XRT86SH221 preliminary 89 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 algorithm 1: step 1: seach for the presence of the correct 7-bit fas pattern. go to step 2 if found; step 2: check if the fas is absent in the following frame by verifying that bit 2 of the assumed tims lot 0 byte is a one. go back to step 1 if verification failed; otherwise, go to step 3; step 3: check if the fas is present in the assumed timeslot 0 byte of the third frame. go back to step 1 if failed. if either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the errored timeslot 0 byte l ocaiton. if both conditions are met and frame check sequence is enabled, then an additional check seque nce is initiated. the check sequence consists of ve rifying correct frame alignment for an additional two frame s. step 4: once the frame alignment is found, check if the fas is absent in the following frame by verify ing the bit 2 of timeslot 0 being a one. if verification failed , go back to step 1. step 5: check that the fas is present of the next f rame. if not, go back to step 1. the second algorithm is similar to the first one, b ut adds a one frame hold-off in the second step to begin a new search in the bit immediately following the second (third frame) assumed fas. this extra frame hold-of f is performed only after the condition in step 2 fails to provide a robust algorithm which allows the fram er to operate correctly in the presence of fixed timeslot imitating the fas pattern. algorithm 2: step 1: seach for the presence of the correct 7-bit fas pattern. go to step 2 if found; step 2: check if the fas is absent in the following frame by verifying that bit 2 of the assumed tims lot 0 byte is a one. go to step 4 if varification failed; otherwi se, go to step 3; step 3: check if the fas is present in the assumed timeslot 0 byte of the third frame. go back to step 1 if failed; otherwise start check sequence if enabled. step 4: wait for assumed fas in next frame, then go back to step 1. if both conditions are met and frame check sequence is enabled, then an additional check sequence is initiated. the check sequence consists of verifyin g correct frame alignment for an additional two fra mes. step 5: once the frame alignment is found, check if the fas is absent in the following frame by verify ing the bit 2 of timeslot 0 being a one. if verification faile d, go back to step 4. step 6: check that the fas is present of the next f rame. if not, go back to step 1. when synchronization is achieved, the framer monito rs alignment signals for errors. a red alarm (fasr ed) is generated if frame alignment is lost. the criter ia for loss of frame alignment in fas framing is di ctated by an e1 framing control register (fcr). the msb of this register is an rsync bit which imposes the framer t o restart the resync process even if the frame is cur rently in sync. this bit will be cleared after the framer resumes its normal sync monitoring mode. the fas cr iteria bits specify the number of consecutive erred fas patterns determining the loss of fas alignment. not e: loss of fas alignment forces loss of cas and los s of crc alignment. it is important to note that the off-line searching is conducted by a shadow synchronizer. the shadow synchronizer continuously searches for the frame al ignment even if the framer is in the in-sync state. once the loss of frame is declared and the resync mode is en tered, the framer can shift back into monitor mode by moving to the new alignment at the beginning of the next frame as long as the shadow synchronizer is i n-sync. this feature dramatically reduces the reframe time required.
preliminary XRT86SH221 90 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu crc synchronization after the fas frame alignment is declared, the seco nd step is to find the crc-4 multiframe alignment. this is done by observing whether the international bits (b it 1 of timeslot 0) of non-fas frames match the crc multiframe alignment pattern. multiframe alignment is declared if at least the valid crc multiframe al ignment signals are observed within 8ms. the crc synchroniz ation logic will force a fas frame search when crc multiframe alignment has not been found for 8ms. once the crc multiframe alignment is found, the out of crc multifame alignment indication is cleared. the crc synchronizer monitors the multiframe alignment signal, indicates errors occurring in the 6-bit crc pattern, and indicates the value of the febe bits ( bit 1 of frames 13 and 15 of the multiframe). the l oss of crc multiframe alignment is declared if consecutive crc multiframe alignment signals have been received in error. when synchronization is achieved, the framer monito rs the multiframe alignment signals for errors. a c rc lof indication is set to "1" if frame alignment is lost. the criteria for loss of crc multiframe align ment is dictated by crcc bits in e1 framing control registe r. annex b compliance when modenb is "1", g.706 annex b modified crc-4 mu ltiframe alignment algorithm is implemented. if crc - 4 alignment is enabled and not achieved in 400ms wh ile the basic frame alignment signal is present, it is assumed that the remote end is a non-crc-4 equipmen t. the flow chart in figure 41 demonstrates this algorithm. f igure 41. f low of crc-4 multiframe alignment for interworking
XRT86SH221 preliminary 91 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 a 400ms crc-4 multiframe alignment search period is applied for interworking detection. the 400 msec t imer is triggered on the initial recovery of basic frame alignment and is not reset until the loss of basic frame alignment occurs. a re-search for fas will be initi ated if crc-4 multifame alignment can not be found in 8ms and will not reset the 400ms timer or invoke the co nsequent actions associated with loss of fas. all subsequent searches for crc-4 multiframe alignment are associated with each basic fas found. in order to maintain no disturbance to traffic during the 400ms crc-4 multiframe search, traffic should be allowed through with synchronization to the initially determined pr imary basic frame alignment sequence. if a crc-4 mu ltiframe alinment signal is found befoe the 400ms timer elap ses, then the basic fas associated with the crc-4 multiframe alignment signal should be the one chose n, i.e. the primary basic fas should be amended accordingly if the basic fas alignment changed. if a crc-4 multiframe alignment sequence can not be fo und in 400ms, it should be concluded that a condition o f interworking between equipments with and without a crc- 4 capability exist, so the traffic should be mainta ined to the initially determined fas alignment. if the path is reconfigured at any time, then it is assumed that the new pair of path will need to re- establish the complete framing process, i.e. the algorithm is res et. consequent actions are taken while a non-crc-4 remo te side is detected: n the framer will provide an indication that there is no incoming crc-4 multiframe alignment signal n the framer will inhibit further crc-4 processing n the framer will continue to transmit crc-4 data to the remote side with both e bits set to zero in this modified framing mode, the framer always se ts the return e bits to zero until the interworking relationship has been established. if crc-4-to-crc- 4 interworking is established, then normal crc-4 processing of erred crc-4 block data should commenc e. if crc-4-to-non-crc-4 interworking is establishe d, the e bits should remain at 0. cas synchronization after the fas frame alignment is declared, the thir d step is to find cas multiframe alignment. two use r- selectable algroithms are available. algorthm 1 monitors the sixteenth timeslot of each frame and declares cas multiframe alignment when 15 consecutive frames with bits 1-4 of timeslot 16 not containing the alignment pattern are observed to p recede a frame with timeslot 16 containing the correct align ment pattern. algorthm 2 monitors the sixteenth timeslot of each frame and declares cas multiframe alignment when no n- zero bits 1-4 of timeslot 16 are observed to preced e a timeslot 16 containing the correct alignment pa ttern. once the cas multiframe alignment is found, the out of cas multifame alignment indication is cleared. the cas synchronizer monitors the multiframe alignment signal, indicates errors occurring in the 4-bit ali gnment pattern, and indicates the debounced value of the r emote signaling multiframe alarm bit (bit 6 of time slot 16 of frame 0 of the multiframe). when synchronization is achieved, the framer monito rs multiframe alignment signals for errors. the cas lof indication turns on if frame alignment is lost. the criteria for loss of crc multiframe alignment is d ictated by the casc bits in the e1 framing control register.
preliminary XRT86SH221 92 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu frame counters and timing generation receive frame and multiframe counters and timing ge nerators provide timing for frame and multiframe alignment, crc-4 check, signaling extraction, facil ity data link extraction, yellow alarm, and all the timing for per-channel parameter fetch. the data extracted fro m this timing is placed into the appropriate intern al storage elements for the microprocessor to access. the info rmation extracted is not valid unless the receive m odule has achieved valid synchronization. crc-4 verification the crc verification is performed by calculating th e 4-bit crc checksum for each incoming sub-multifra me and comparing this result to the received crc remai nder bits in the subsequent sub-multiframe. the crc errors are accumulated over one second intervals. o ptionally, a crc frame resync can be initiated when 915 or more crc errors occur in one second. the number of crc errors accumulated during the previous secon d is available by reading the e1 receive synchronizat ion bit error counter. alarm and error indication the alarm indication logic examines the incoming e1 data for alarm conditions. when the change of an a larm condition is detected, corresponding bits are set i n the alarm and error status register. the alarm an d error interrupt enable register is used to select the eve nts that generate interrupts on the microprocessor interrupt pin when their state changes. lof (red alarm) defect/alarm when defdet=1, the loss of frame defect is detected when "fasc" (in framing control register) consecut ive incorrect frame alignment signals have been receive d (default is 3 to comply with g.706). it is clear ed when 2 consecutive fas's are detected. when defdet = 0, the red alarm is detected by monit oring the occurrence of loss of frame (lof) over a 4 ms interval. an lof valid flag will be posted on t he interval when one or more lof occurred during th e interval. each interval with a valid lof flag incr ements a flag counter which declares red alarm when 25 valid intervals have been accumulated. an interval witho ut valid lof flag decrements the flag counter. the red alarm is removed when the counter reaches zero. transmit slip buffering the voyager-lite has two-frame (512 bits) elastic s tores. this store can be enabled or disabled via programming bits sb_enb in the slip buffer control and status register (sbcsr). if the elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties and a read occurs, then a full f rame of data will be repeated and a status bit will be updated. if th e buffer fills and a write comes, then a full frame of data will be deleted and another status bit will be set. if the slip buffer is bypassed (sb_enb[1:0] = 00 or 11), the slip buffer is used as a regular ja buffer. if sb_enb = 2, the slip buffer is put into a fifo mode. in the fifo mo de, the slip buffer is acting like a standard first-in-firs t-out storage. a fixed read and write latency is ma intained in a programmable fashion controlled by the fifo latency register. however, the user should assume the responsibility to phase lock the input clock to the receive clock to avoid either overrun or under-run . a slip buffer control & status register is used to control the slip buffer operations and control interrupts and report its status.
XRT86SH221 preliminary 93 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 4.11 e1 phy loopback diagnostics this section provides some architectural views and implementation details regarding to the system leve l integration and performance. 4.11.1 e1 loopbacks various controls in the vt mapper module and e1 fra mer module allow voyager-lite to conduct many types of loopbacks for supporting system diagnosis. three of them are explained here: e1 facility loopback, e1 facility i/ o loopback and e1 module loopback. e1 facility loopback figure 42 shows this type of loopback by sending the ingress e1 inputs back to egress e1 outputs. f igure 42. e1 f acility l oopback sdh
preliminary XRT86SH221 94 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 4.11.2 e1 facility i/o loopback figure 43 shows the this type of loopback by connecting the egress e1 outputs to the ingress e1 inputs. f igure 43. e1 f acility i/o l oopback
XRT86SH221 preliminary 95 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 4.11.3 e1 module loopback figure 44 shows the this type of loopback by sending the ing ress e1 framer outputs back to egress e1 framer inputs. f igure 44. e1 module l oopback
preliminary XRT86SH221 96 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 4.11.4 alarm and auto ais voyager-lite provides the capability to insert alar m, especially ais, automatically into the data down stream while exceptional conditions occur. figure 45 shows the basic structure of the auto ais insertio n. note: each condition is optional f igure 45. e1 a uto ais i nsertion t able 13: e1 to stm-0 - response time < 125 u s e1 c ondition stm-0 r esponse los e1-ais,pdi-p/ais-p lof pdi-p/ais-p ais-l pdi-p/ais-p t able 14: stm-0 to e1 - response time < 125 usec stm-0 c ondition e1 r esponse stm-0 r eturn path los e1 ais rdi-l, rdi-p lof e1 ais rdi-l, rdi-p ais-l e1 ais rdi-l, rdi-p auto c2 insertion and sts-1/vt auto ais insertion rx vt mapper n1,n2 ais siglabel_mis enb_mflof mflof enb_apid tc_apid tc_uneq enb_uneq enb_vt_tu vt_tu ais enb_uneq uneq enb_siglabel enb_n1,n2 ais enb_j2_inv,j2_mis j2_inv,j2_mis mode involved vt 28 1 28 enb_sd enb_sf sf sd uneq-p enb_pdi-p c2=fc enb_lcd-p lcd-p tim-p enb_uneq-p enb_lop-p enb_plm-p enb_tim-p lop-p plm-p enb_ais-p ais-p rxpoh rxtoh ais-l los enb_lof lof enb_ais-l enb_los stm-0 stm-0 txpoh stm-0 mode involved sdh ins pdi-p (c2) ingress egress e1 terminator l2 e1 21 enb_lof lof ins ais using clock w/ standard freq. l2 e1 tx e1 tx w/ standard freq. using clock ins ais mode involved liu extlos ingress egress enb_lof e1 terminator e1 1 l2 lof ins ais using clock w/ standard freq. l2 e1 tx using clock w/ standard freq. e1 tx ins ais mode involved liu extlos
XRT86SH221 preliminary 97 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 lop-p e1 ais rdi-p ais-p e1 ais rdi-p uneq-p e1 ais rdi-p plm-p e1 ais rdi-p tim-p e1 ais rdi-p t able 14: stm-0 to e1 - response time < 125 usec stm-0 c ondition e1 r esponse stm-0 r eturn path
preliminary XRT86SH221 98 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 5.0 analog front end / line interface unit (liu) sec tion the analog front end section is a fully integrated, 21-channel e1 liu for 75 w or 120 w applications. with internal termination and an option for high impedan ce, the liu uses one bill of materials to support c oax or twisted pair medium and supports 1:1 or 1+1 redunda ncy. each transmitter has an optional jitter attenu ator and can provide basic diagnostic features that can be used to send data to the line interface. each re ceiver accepts standard e1 pulses, provides clock and data recovery, basic diagnostic detection, and an optio nal jitter attenuator before presenting data to the vt mapper section. a simplified block diagram of the l iu section can be seen below. f igure 46. s implified b lock d iagram of the liu s ection line driver tx pulse shaper & pattern gen timing control tx / rx jitter attenuator tx / rx jitter attenuator clock & data recovery peak detector & slicer driver monitor ais & los detector qrss generation & detection remote lb digital lb analog lb tclk tpos rclk rpos ttip tring rtip rring vt mapper section
XRT86SH221 preliminary 99 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 5.1 transmit line interface unit 5.1.1 jitter attenuator the liu is ideal for multiplexer or mapper applicat ions where the network data crosses multiple timing domains. as the higher data rates are de-multiplex ed down to e1 data, stuffing bits are typically rem oved which can leave gaps in the incoming data stream. the jitter attenuator can be selected in the transm it path with a 32-bit or 64-bit fifo that is used to smooth the gapped clock into a steady e1 output. the max imum gap width that the jitter attenuator can accept wit hout a disruption in data flow is shown below. n ote : if the liu is used in a loop timing system, the jit ter attenuator can be selected in the receive path. see the receive liu section of this datasheet. 5.1.2 taos (transmit all ones) the liu section has the ability to transmit all one s on a per channel basis by programming the appropr iate channel register. this function takes priority over the digital data present on its digital inputs fro m the vt mapper section. figure 47 is a diagram showing the all ones signal at ttip a nd tring. f igure 47. taos (t ransmit a ll o nes ) 5.1.3 ataos (automatic transmit all ones) if ataos is selected by programming the appropriate global register, an ami all ones signal will be tr ansmitted for each channel that experiences an rlos condition . if rlos does not occur, the ataos will remain in active until an rlos on a given channel occurs. a simplifi ed block diagram of the ataos function is shown in figure 48 . f igure 48. s implified b lock d iagram of the ataos f unction fifo d epth m aximum g ap w idth 32-bit 20 ui 64-bit 50 ui taos 1 1 1 rlos ataos taos ttip tring tx
preliminary XRT86SH221 100 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 5.1.4 qrss/prbs generation the liu section can transmit a qrss/prbs random seq uence to a remote location from ttip/tring. to select qrss or prbs, see the register map for progr amming details. the polynomial for each selection is shown below. 5.1.5 transmit pulse shaper and filter if tclk is not present from the vt mapper section, pulled "low", or pulled "high" the transmitter outp uts at ttip/tring will automatically send an all ones or a n all zero signal to the line by programming the ap propriate global register. by default, the transmitters will send all zeros. to send all ones, the tclkcnl bit must be set "high". 5.1.6 dmo (digital monitor output) the driver monitor circuit is used to detect transm it driver failures by monitoring the activities at the ttip/ tring outputs. driver failure may be caused by a sh ort circuit in the primary transformer or system pr oblems at the transmit inputs. if the transmitter of a cha nnel has no output for more than 128 clock cycles, dmo goes "high" until a valid transmit pulse is detected. if the dmo interrupt is enabled, the change in status of dmo will cause the interrupt pin to go "low". once the statu s register is read, the interrupt pin will return " high" and the status register will be reset (rur). 5.2 line termination (ttip/tring) the output stage of the transmit path generates sta ndard return-to-zero (rz) signals to the line inter face for e1 twisted pair or e1 coaxial cables. the physical int erface is optimized by placing the terminating impe dance inside the liu. this allows one bill of materials f or 75 w and 120 w reducing the number of external components necessary in system design. the transmitter outputs only require one dc blocking capacitor of 0.68 m f. for redundancy applications (or simply to tri-state the transmitters), set txtsel to a "1" in the appropri ate channel register. a typical transmit interface is shown in figure 49 . f igure 49. t ypical c onnection d iagram u sing i nternal t ermination r andom p attern e1 qrss 2 20 - 1 prbs 2 15 - 1 t tip t ring 1:2 internal impedance e1 line interface c=0.68uf transmitter output
XRT86SH221 preliminary 101 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 5.3 receive path line interface the receive path of the liu section consists of 21 independent e1 receivers. the following section des cribes the complete receive path from rtip/rring inputs to rclk/rpos outputs which are then sent to the vt mapper interface internal to the chip. a simplified block diagram of the receive path is shown in figure 50 . f igure 50. s implified b lock d iagram of the r eceive p ath 5.3.1 line termination (rtip/rring) the input stage of the receive path accepts standar d e1 twisted pair or coaxial cable inputs through r tip and rring. the physical interface is optimized by placi ng the terminating impedance inside the liu. this a llows one bill of materials for 75 w and 120 w operation reducing the number of external componen ts necessary in system design. the receive termination impedance (a long with the transmit impedance) is selected by programming tersel to match the line impedance. sel ecting the internal impedance is shown below. the liu section has the ability to switch the inter nal termination to "high" impedance by programming rxtsel in the appropriate channel register. for internal t ermination, set rxtsel to "1". by default, rxtsel i s set to "0" ("high" impedance). see figure 51 for a typical connection diagram using the interna l termination. f igure 51. t ypical c onnection d iagram u sing i nternal t ermination tersel l ine t ermination 0 75 w 1 120 w rx jitter attenuator clock & data recovery peak detector & slicer rtip rring rclk rpos r tip r ring 1:1 internal impedance e1 line interface receiver input
preliminary XRT86SH221 102 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 5.3.2 clock and data recovery the receive clock (rclk) is recovered by the clock and data recovery circuitry. an internal pll locks on the incoming data stream and outputs a clock thats in phase with the incoming signal. this allows for mul ti- channel e1 signals to arrive from different timing sources and remain independent. in the absence of a n incoming signal, rclk maintains its timing by using the internal master clock (64 x e1) as its referen ce (mclk). once, rlos is cleared, the recovered line c lock switches back to rclk. see figure 52 for the detailed timing specifications. f igure 52. r ecovered l ine c lock pll t iming n ote : 1. vdd=3.3v 5%, t a =25c, unless otherwise specified n ote : 2. rlos declaration and clearance depends on which mode is selected. the liu supports both g.775 and e tsi- 300-233. refer to the register map for more details . 5.3.3 recovered line clock outputs there are two output pins that can be used to selec t among the 21 recovered line clock signals. these signals can be used as a timing reference relative to the two channels chosen. the pins are ref_rec1 a nd ref_rec0. p arameter s ymbol m in t yp m ax u nits switching time from rclk to mclk t 1 14.6 m s rlos declares loss of signal t 2 see note 2. rlos clears loss of signal t 3 see note 2 switching time from mclk to rclk t 4 18.1 m s f igure 53. ref_rec[1:0] r ecovered l ine c lock s election to o utput p ins valid data rclk rpos rlos valid data loss of data switch to mclk t 1 t 2 t 3 t 4 multiplexer ref_clk1 ref_clk0 21 recovered line clocks clock and data recovery 21 channel liu inputs register selection 21:2
XRT86SH221 preliminary 103 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 5.3.4 rlos (receiver loss of signal) the liu section supports both g.775 or etsi-300-233 rlos detection. in g.775 mode, rlos is declared when the received s ignal is less than 375mv for 32 consecutive pulse periods (typical). the device clears rlos when the receive signal achieves 12.5% ones density with no more than 15 consecutive zeros in a 32 bit sliding windo w and the signal level exceeds 425mv (typical). in etsi-300-233 mode, the device declares rlos when the input level drops below 375mv (typical) for mo re than 2048 pulse periods (1msec). the device exits rlos when the input signal exceeds 425mv (typical) and has transitions for more than 32 pulse periods with 12.5% ones density with no more than 15 consecutive zeros in a 32 bit sliding wind ow. 5.3.5 exlos (extended loss of signal) by enabling the extended loss of signal by programm ing the appropriate channel register, the digital r los is extended to count 4,096 consecutive zeros before de claring rlos. by default, exlos is disabled and rlo s operates in normal mode. 5.3.6 jitter attenuator the jitter attenuator reduces phase and frequency j itter in the recovered clock if it is selected in t he receive path. the jitter attenuator uses a data fifo (first in first out) with a programmable depth of 32-bit or 64-bit. if the liu is used for line synchronization (loop timi ng systems), the ja should be enabled in the receiv e path. when the read and write pointers of the fifo are wi thin 2-bits of over-flowing or under-flowing, the b andwidth of the jitter attenuator is widened to track the sh ort term input jitter, thereby avoiding data corrup tion. when this condition occurs, the jitter attenuator will not at tenuate input jitter until the read/write pointers position is outside the 2-bit window. the bandwidth is programm able to either 10hz or 1.5hz (1.5hz automatically s elects the 64-bit fifo depth). the ja has a clock delay eq ual to ? of the fifo bit depth. n ote : if the liu is used in a multiplexer/mapper applicat ion where stuffing bits are typically removed, the jitter attenuator can be selected in the transmit path to smooth out the gapped clock. see the transmit liu section of this datasheet. 5.3.7 rxmute (receiver los with data muting) the receive muting function can be selected by sett ing rxmute to "1" in the appropriate global registe r. if selected, any channel that experiences an rlos cond ition will automatically pull rpos "low" to prevent data chattering to the internal connection to the vt map per section. if rlos does not occur, the rxmute wil l remain inactive until an rlos on a given channel oc curs. the default setting for rxmute is "0" which i s disabled. a simplified block diagram of the rxmute function is shown in figure 54 . f igure 54. s implified b lock d iagram of the r x mute f unction rlos rxmute rpos
preliminary XRT86SH221 104 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 6.0 memory and register map this section provides a complete list of the voyage r-lite register address map as an over view followe d by a full description of each register. 6.1 memory mapped i/o addressing in order to support a multiple channel implementati on, maintain rich user controlled features, and pro vide future scalability without sacrificing performance for microcontroller access, voyager-lite chooses an addressing scheme to channelize the access for the microcontroller interface. this mapping scheme was chosen such that voyaer-lite is compatible with its 28 channel predecessor, voyager xrt86sh328 which also supports ds1, ds-3, m13 mux, sts-1/sts-3 sonet framer/vt mapper and many other features. 6.2 overview of control registers t able 15: c hannel m apping s cheme n c hannels 1-3 channel 1 through channel 3 5-7 channel 4 through channel 6 9-11 channel 7 through channel 9 13-15 channel 10 through channel 12 17-19 channel 13 through channel 15 21-23 channel 16 through channel 18 25-27 channel 19 through channel 21 t able 16: m emory m ap - e1 f ramers a ddress c ontents 0x0001 - 0x004f sdh operation control 0x0202 - 0x027f receive toh block 0x0281 - 0x02f3 receive poh block au-3 n ote : when 0x02 is replaced with 0x05, the part is processing au-4. (0x0581 - 0x05f3) 0x0700 - 0x0753 transmit toh block 0x0781 - 0x07d3 transmit poh block au-3 n ote : when 0x07 is replaced with 0x0a, the part is processing au-4. (0x0a81 - 0x0ad3) 0xn000 - 0xn011 e1 line interface unit 0xn100 - 0xnb01 e1 receive synchronizer framer 0xnc03 - 0xnf3f vt mapping operation control
XRT86SH221 preliminary 105 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 6.3 sdh operation control register descriptions bit [7:3] - reserved bit 2 - interrupt type select: this bit is used to select between reset-upon-read or write-1-to-clear 0 - rur 1 - wc bit 1 - clear interrupt enable after read this bit is used to select the auto-clear function that will reset all the interrupt enable bits back to their default values. 0 - interrupt enable bit is not cleared after statu s reading. 1 - interrupt enable bit is cleared after status re ading. bit 0 - interrupt generation enable this bit is used to select between an interrupt gen eration or status polling (no int) environment. 0 - status polling 1 - interrupt generation enabled bit 7 - reserved bit 6 - receive stm-x clock detect this bit allows the transmit clock output to be loo ped back to the receive clock input in the event th at the receive clock is missing. 0 - disabled 1 - enabled bit [5:1] - reserved bit 0 - sdh block software reset this bit is used to reset the internal circuitry of the entire sdh blocks to their default state. this bit does not reset any register bits. 0 - normal operation 1 - sdh software reset t able 17: i nterrupt t ype s elect (its 0 x 0001 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved int_sel clear_int int_gen r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 18: r eceive stm c lock d etect (rstmcd 0 x 0003 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved rxsclkdet reserved sdh_rst r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 106 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - device id the contents of this read only register should alwa ys be set to 0x51h. the purpose of this register is for identification only. bit [7:0] - device id the contents of this read only register should be s et to 0x01h for revision a silicon. the purpose of this register is for revision identification only. bit [7:1] - reserved bit 0 - telecom bus parity interrupt enable this bit is used to enable parity interrupt while c onfigured to operate in the telecom bus mode. 0 - disabled 1 - parity interrupt enabled t able 19: d evice id r egister (devid 0 x 0004 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 devid[7:0] ro ro ro ro ro ro ro ro 0 1 0 1 0 0 0 1 t able 20: r evision id r egister (revid 0 x 0005 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 revid[7:0] ro ro ro ro ro ro ro ro 0 0 0 0 0 0 0 1 t able 21: t elecom b us p arity e nable (tbpe 0 x 000b h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved tbpinten r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 107 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:1] - reserved bit 0 - telecom bus parity error interrupt enable this bit is used to enable parity interrupt while c onfigured to operate in the telecom bus mode. 0 - disabled 1 - parity error interrupt enabled bit 7 - operation control interrupts including tele com bus interrupts operation control block interrupt for all interrupt s in operation control register address map includi ng telecom bus and aps interrupts. when 1, an interrupt is pending. bit 6 - reserved bit 5 - vt mapper block interrupt. when 1, an interrupt from the vt mapper block is pe nding. bit 4 - reserved bit 3 - e1 framing synchronizer block interrupt. when 1, an interrupt from the e1 framing synchroniz er block is pending. bit 2 - reserved bit 1 - receive line interface block interrupt. when 1, an interrupt from the receive line interfac e block is pending. bit - 0 transmit line interface block interrupt. when 1, an interrupt from the transmit line interfa ce block is pending. t able 22: t elecom b us p arity e rror e nable (tbpee 0 x 000f h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved tbperr_en r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 23: o peration b lock i nterrupt r egister 1 (opir1 0 x 0012 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 op_cntl reserved vtmapper reserved e1 reserved rxliu txliu ro ro ro ro ro ro ro ro 0 0 0 0 0 0 0 0
preliminary XRT86SH221 108 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - reserved bit 6 - receive sdh transport overhead block interr upt when 1, an interrupt from the sdh toh block is pend ing. bit 5 - receive sdh path overhead block interrupt when 1, an interrupt from the sdh poh block is pend ing. bit [4:3] - reserved bit 2 - external interrupt input 1 when 1, an interrupt from the ext_int_1 pin is pend ing. bit 1 - external interrupt input 0 when 1, an interrupt from the ext_int_0 pin is pend ing. bit 0 - reserved t able 24: o peration b lock i nterrupt r egister b yte 0 (opir0 0 x 0013 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved rxstoh rxspoh reserved extint1 extint0 reserved ro ro ro ro ro ro ro ro 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 109 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - operation control block interrupt enable when 0, interrupts are disabled. when 1, interrupts are enabled. bit 6 - reserved bit 5 - vt mapper block interrupt enable when 0, interface interrupts are disabled. when 1, interrupts are enabled. bit 4 - reserved bit 3 - e1synchronizer block interrupt enable when 0, interrupts are disabled. when 1, interrupts are enabled. bit 2 - reserved bit 1 - receive line interface block interrupt enab le when 0, receive line interface interrupts are disab led. when 1, receive line interface interrupts are enabl ed. bit 0 - transmit line interface block interrupt ena ble when 0, receive line interface interrupts are disab led. when 1, receive line interface interrupts are enabl ed. t able 25: o peration b lock i nterrupt e nable r egister b yte 1 (opier1 0 x 0016 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 op_cntl_e reserved vtmap_enb reserved e1_enb reserved rxl iu_enb txliu_enb r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 110 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - reserved bit 6 - receive sdh transport overhead block interr upt enable when 0, receive transport overhead interrupts are disabled. when 1, receive stoh interrupts are enabled. bit 5 - receive sdh path overhead block interrupt e nable when 0, receive path overhead interrupts are disabl ed. when 1, receive spoh interrupts are enabled. bit [4:3] - reserved bit 2 - external interrupt input 1 interrupt enable when 0, the interrupts is disabled. when 1, the interrupt is enabled. bit 1 - external interrupt input 0 interrupt enable when 0, the interrupts is disabled. when 1, the interrupt is enabled. bit 0 - reserved bit 7 - de-sync disable this bit is used to disable the de-sync function fo r all egress e1 line outputs. 0 - normal de-sync function 1 - disabled bit [6:1] - reserved bit 0 - au3 mapping enable this bit is used to select au3 mapping instead of t ug3. 0 - tug3 mapping 1 - au3 mapping t able 26: o peration b lock i nterrupt e nable r egister b yte 0 (opier0 0 x 0017 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved rxtoh_enb rxpoh_enb reserved extint1_en extint0 _en reserved r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 27: d e -s ync and au3 m apping c ontrol (dsau3mc 0 x 001b h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dsync_dis reserved au3_en r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 111 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:4] - reserved bit [3:0] - sdh loop back select these bits are used to select the sdh loop back mod e for diagnostic testing. 0000 - no loop back 0001 - reserved 0010 - local transport lb (toh, poh, and payload) 0011 - local path lb (poh and payload) 11xx - reserved bit [7:0] - high byte of the frame boundary latency [15:8] this bit is used to determine the latency between t he frame sync input pulse to the first byte of the sdh frame out of this device. bit [7:0] - low byte of the frame boundary latency [7:0] this bit is used to determine the latency between t he frame sync input pulse to the first byte of the sdh frame out of this device. t able 28: sdh l oop b ack s elect (sdhlbs 0 x 001f h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved sdhloop[3:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 29: h igh b yte f rame b oundary l atency (hbfbl 0 x 0034 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hb_fb_latency[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 30: l ow b yte f rame b oundary l atency (lbfbl 0 x 0035 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lb_fb_latency[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 112 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - telecom bus rate select this bit is used to select between stm-0 or stm-1 w hile in the telecom bus mode. 0 - stm-1 19.44 mhz 1 - stm-0 6.48 mhz bit 6 - empty time slot select if this chip is configured as the master device in stm-1, this bit is used to determine the state of t he parallel data within the two empty slots on the shared telecom bus. 0 - two empty slots are filled with all zeros 1 - two empty slots are tri-stated bit 5 - slot 0 master frame pulse select the state of this bit determines if the chip is the master device or slave device. 0 - frame pulse is an input (slave device) 1 - frame pulse is an output (master device) bit [4:3] - time slot select these bits indicate the time slot number on the tel ecom bus where this chip resides if it's configured to tri-state the two empty slots. the master device "must" occupy time s lot 0. 00 - time slot 0 01 - time slot 1 10 - time slot 2 11 - reserved bit 2 - v5path over head parity enable this bit is used to enable v5 in the parity generat ion and checking. 0 - disabled 1 - v5poh enabled bit 1 - fp_enb this bit is used to configure the telecom bus as a parallel port and only clock, data and frame pulse (c1j1 signal) are valid signals. 0 - normal operation 1 - fp enabled bit 0 - v5 path over head enable this bit is used to enable the v5 poh byte. 0 - disabled 1 - v5 poh enabled t able 31: t elecom b us c ontrol 1 (tbc1 0 x 0036 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tbrate empty_ts mst_fp ts_sel[1:0] v5pohpe fp_en v5pohe r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 113 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - telecom bus enable this bit is used to enable the telecom bus. by defa ult, this bit is set to 1 (enabled). 0 - disabled 1 - enabled bit 6 - telecom bus tri-state this bit is used to tri-state the telecom bus. 0 - normal operation 1 - tri-stated bit 5 - frame pulse operates at 2khz this bit is used to enable v1 alignment which sets the frame pulse at a rate of 2khz. 0 - normal rate 1 - frame pulse is 2khz bit 4 - telecom bus parity select this bit is used to select which data is used for p arity generation and check. 0 - data bits only 1 - data bits, c1j1, and pl bit 3 - telecom bus j1 only this bit determines the usage of the telecom bus wh ile the c1j1v1_fp signal generates c1j1 pulse or ju st j1 pulse. 0 - both c1 and j1 pulses are generated 1 - only j1 pulse is generated bit 2- telecom bus parity select this bit determines whether the parity is odd or ev en for the telecom bus. 0 - even parity 1 - odd parity bit 1- telecom bus parity enable this bit determines whether parity generation and c hecking are enabled on the telecom bbus. 0 - parity enabled 1 - parity disabled bit 0 - re-phase on this bit determines the usage of the telecom bus wh ile it is selected as rephase/sync interface in tel ecom bus mode. in re-phase off mode, frame synchronization is gain ed from the data stream. in re-phase on mode, the s dh framer block uses the c1j1v1_fp for "re-phasing" frame ali gnment to the external frame pulse pin. 0 - re-phase off 1 - re-phase on t able 32: t elecom b us c ontrol 0 (tbc0 0 x 0037 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tb_en tb_high-z fp2khz tbp_sel j1_only tbpar_sel tbpar_en re-phase r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 114 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - general purpose input/output these bits either generate or monitor the activity on the hardware pins according to the direction. bit [7:0[] - general purpose i/o direction select these bits are used to set the direction of the gpi o hardware pins. 0 - inputs 1 - outputs bit [7:5] - reserved bit [4:0] - recovered clock select 0 these bits select one of the 21 recovered e1 clocks to output on rclk_rec0 output pin. see table 37 . bit [7:5] - reserved bit [4:0] - recovered clock select 1 these bits select one of the 21 recovered e1 clocks to output on rclk_rec1 output pin. see table 37 . t able 33: g eneral p urpose i nput /o utput (gpio 0 x 0047 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 gpio[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 34: g eneral p urpose i nput /o utput d irection (gpiod 0 x 004b h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 gpio_dir[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 35: r ecovered l ine c lock r eference 1 (rlcr1 0 x 004d h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved recclk_sel0[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 36: r ecovered l ine c lock r eference 0 (rlcr0 0 x 004e h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved recclk_sel1[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 115 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 t able 37: r ecovered l ine c lock s elect for rclk_rec1 and rclk_rec0 h ardware p ins bit[4:0] r ecovered l ine c lock c hannel 00000 tri-state 00001 channel 0 00010 channel 1 00011 channel 2 00100 channel 3 00101 channel 4 00110 channel 5 00111 channel 6 01000 channel 7 01001 channel 8 01010 channel 9 01011 channel 10 01100 channel 11 01101 channel 12 01110 channel 13 01111 channel 14 10000 channel 15 10001 channel 16 10010 channel 17 10011 channel 18 10100 channel 19 10101 channel 20 10110 - 11111 tri-state
preliminary XRT86SH221 116 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:3] - reserved bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1 slot bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding e1 slot bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1 slot bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding e1 slot bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1 slot bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding e1 slot bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1 slot t able 38: c hannel i nterrupt i ndication r egister 11 (chiir11 0 x 0054 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_slot[20:18] r r r r r r r r 0 0 0 0 0 0 0 0 t able 39: c hannel i nterrupt i ndication r egister 10 (chiir10 0 x 0055 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_slot[17:15] reserved e1_slot[14:12] r r r r r r r r 0 0 0 0 0 0 0 0 t able 40: c hannel i nterrupt i ndication r egister 9 (chiir9 0 x 0056 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_slot[11:9] reserved e1_slot[8:6] r r r r r r r r 0 0 0 0 0 0 0 0 t able 41: c hannel i nterrupt i ndication r egister 8 (chiir8 0 x 0057 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_slot[5:3] reserved e1_slot[2:0] r r r r r r r r 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 117 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:3] - reserved bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1 liu channel slo t bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding e1 liu channel slo t bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1liu channel slo t bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding e1 liu channel slo t bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1 liu channel slo t bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding e1 liu channel slo t bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding e1 liu channel slo t t able 42: c hannel i nterrupt i ndication r egister 7 (chiir7 0 x 0058 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_liu_slot[20:18] r r r r r r r r 0 0 0 0 0 0 0 0 t able 43: c hannel i nterrupt i ndication r egister 6 (chiir6 0 x 0059 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_liu_slot[17:15] reserved e1_liu_slot[14:12 ] r r r r r r r r 0 0 0 0 0 0 0 0 t able 44: c hannel i nterrupt i ndication r egister 5 (chiir5 0 x 005a h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_liu_slot[11:9] reserved e1_liu_slot[8:6] r r r r r r r r 0 0 0 0 0 0 0 0 t able 45: c hannel i nterrupt i ndication r egister 4 (chiir4 0 x 005b h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e1_liu_slot[5:3] reserved e1_liu_slot[2:0] r r r r r r r r 0 0 0 0 0 0 0 0
preliminary XRT86SH221 118 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:3] - reserved bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding vt channel slot. bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding vt channel slot. bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding vt channel slot. bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding vt channel slot. bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding vt channel slot. bit [6:4] - each bit indicates an interrupt has bee n generated by the corresponding vt channel slot. bit [2:0] - each bit indicates an interrupt has bee n generated by the corresponding vt channel slot. t able 46: c hannel i nterrupt i ndication r egister 3 (chiir3 0 x 005c h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved vt_slot[20:18] r r r r r r r r 0 0 0 0 0 0 0 0 t able 47: c hannel i nterrupt i ndication r egister 2 (chiir2 0 x 005d h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved vt_slot[17:15] reserved vt_slot[14:12] r r r r r r r r 0 0 0 0 0 0 0 0 t able 48: c hannel i nterrupt i ndication r egister 1 (chiir1 0 x 005e h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved vt_slot[11:9] reserved vt_slot[8:6] r r r r r r r r 0 0 0 0 0 0 0 0 t able 49: c hannel i nterrupt i ndication r egister 0 (chiir0 0 x 005f h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved vt_slot[5:3] reserved vt_slot[2:0] r r r r r r r r 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 119 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 6.4 receive transport overhead operation control reg ister descriptions bit [7:3] - unused bit 2 - sync on b1 this bit is used to enable b1 verification as part of the synchronization process. sync_on_b1 can only be declared after 2 consecutive correct b1 bytes after a1 and a 2 have been identified. 0 - disabled 1 - enabled bit 1 - unused bit 0 - no overhead data extract this bit is used to disable toh extraction. by defa ult, toh extraction is enabled. 0 - toh extraction occurs 1 - toh extraction disabled bit 7 - unused bit 6 - signal failure (sf) defect condition detect enable this read/write bit-field is used to enable or disa ble sf defect detection and declaration by the rece ive stm-0/ stm-1 toh processor block. 0 - configures the receive stm-0/stm-1 toh processo r block to not declare nor clear the sf defect cond ition per the user-specified sf defect declaration and cleara nce criteria. 1 - configures the receive stm-0/stm-1 toh processo r block to declare and clear the sf defect conditio n per the user-specified sf defect declaration and clearance criteria. bit 5 - signal degrade (sd) defect condition detect enable this read/write bit-field is used to enable or disa ble sd detection and declaration by the receive stm -0/stm-1 toh processor block. 0 - configures the receive stm-0/stm-1 toh processo r block to not declare nor clear the sd defect cond ition per the user-specified sd defect declaration and cleara nce criteria. 1 - configures the receive stm-0/stm-1 toh processo r block to declare and clear the sd defect conditio n per the user-specified sd defect declaration and clearance criteria. bit 4 - de-scramble disable t able 50: r eceive stm-0/stm-1 t ransport c ontrol r egister 1 (rtcr1 = 0 x 0202) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused sync on b1 unused no oh extract r/o r/o r/o r/o r/o r/w r/o r/w 0 0 0 0 0 0 0 0 t able 51: r eceive stm-0/stm-1 t ransport c ontrol r egister 0 (rtcr0 = 0 x 0203) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused sf defect condition detect enable sd defect condition detect enable descramble- disable sonet/sdh rei-lerror type b2 errortype b1 error type r/o r/w r/w r/w r/o r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 120 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu this read/write bit-field is used to either enable or disable de-scrambling by the receive stm-0/stm-1 toh processor block, associated with channel n. 0 - de-scrambling is enabled. 1 - de-scrambling is disabled. bit 3 - sonet/sdh select this bit is used to select between sonet processing or sdh processing. 0 - sonet processing 1 - sdh processing bit 2 - rei-l error type this read/write bit-field is used to specify how th e receive stm-0/stm-1 toh processor block will coun t (or tally) rei-l events, for performance monitoring purposes. the user can configure the receive stm-0/stm-1 toh processor block to increment rei-l events on either a per-bit or per-frame basis. if the user configures the receive stm-0/stm-1 toh processor block to increment rei-l events on a per- bit basis, then it will incrememt the receive stm-0/stm-1 tran sport rei-l error count register by the value of th e lower nibble within the m0/m1 byte of the incoming stm-0 data-st ream. if the user configures the receive stm-0/stm-1 toh processor block to increment rei-l events on a per- frame basis, then it will increment the receive stm-0/stm-1 tran sport rei-l error count register each time it recei ves an stm-0 or stm-1 frame, in which the lower nibble of the m0 /m1 byte is set to a non-zero value. 0 - configures the receive stm-0/stm-1 toh processo r block to count or tally rei-l events on a per-bit basis. 1 - configures the receive stm-0/stm-1 toh processo r block to count or tally rei-l events on a per-fra me basis. bit 1 - b2 error type this read/write bit-field is used to specify how th e receive stm-0 toh processor block will count (or tally) b2 byte errors, for performance monitoring purposes. the u ser can configure the receive stm-0 toh processor b lock to increment b2 byte errors on either a per-bit or a p er-frame basis. if the user configures the receive stm-0 toh proces sor block to increment b2 byte errors on a per-bit basis, then it will increment the receive transport b2 byte error count register by the number of bits (within the b2 byte value) that is in error. if the user configures the receive stm-0 toh proces sor block to increment b2 byte errors on a per-fram e basis, then it will increment the receive transport b2 byte err or count register each time it receives an stm-0 fr ame that contains an erred b2 byte. 0 - configures the receive stm-0 toh processor bloc k to count b2 byte errors on a per-bit basis. 1 - configures the receive stm-0 toh processor bloc k to count b2 byte errors on a per-frame basis. bit 0 - b1 error type this read/write bit-field is used to specify how th e receive stm-0 toh processor block will count (or tally) b1 byte errors, for performance monitoring purposes. the u ser can configure the receive stm-0 toh processor b lock to increment b1 byte errors on either a per-bit or per -frame basis. if the user configures the receive stm-0 toh proces sor block to increment b1 byte errors on a per-bit basis, then it will increment the receive transport b1 byte error count register by the number of bits (within the b1 byte value) that is in error. if the user configures the receive stm-0 toh proces sor block to increment b1 byte errors on a per-fram e basis, then it will increment the receive transport b1 byte err or count register each time it receives an stm-0 fr ame that contains an erred b1 byte. 0 - configures the receive stm-0 toh processor bloc k to count b1 byte errors on a per-bit basis. 1 - configures the receive stm-0 toh processor bloc k to count b1 byte errors on a per-frame basis.
XRT86SH221 preliminary 121 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:3] - unused bit 2 - section trace message mismatch defect decla red this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the section trace mismatch defect condition. the recei ve stm-0 toh processor block will declare the secti on trace message mismatch defect condition, whenever it acce pts a section trace message (via the j0 byte, withi n the incoming stm-0 data-stream) that differs from the expected s ection trace message. 0 - indicates that the section trace message mismat ch defect condition is not currently being declared . 1 - indicates that the section trace message mismat ch defect condition is currently being declared. bit 1 - section trace message unstable defect decla red this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the sec- tion trace message unstable defect condition. the receive stm-0 toh processor block will declare the section trace message unstable defect condition, whenever the sec tion trace message unstable counter reaches the val ue 8. the section trace message unstable counter will be incremented for each time that it receives a sectio n trace message that differs from the expected section trace messag e. the section trace message unstable counter is clear ed to 0 whenever the receive stm-1 toh processor bl ock has received a given section trace message 3 (or 5) con secutive times. n ote : receiving a given section trace message 3 (or 5) co nsecutive times also sets this bit-field to 0. 0 - section trace message unstable defect condition is not currently being declared. 1 - section trace message unstable defect condition is currently being declared. bit 0 - ais-l defect declared this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the ais-l (line ais) defect condition. the receive stm -0 toh processor block will declare the ais-l defec t condition within the incoming stm-0 data stream if bits 6, 7 and 8 (e.g., the least significant bits, within the k2 byte) are set to the value [1, 1, 1] for five consecutive stm-0 fram es. 0 - indicates that the ais-l defect condition is no t currently being declared. 1 - indicates that the ais-l defect condition is cu rrently being declared. t able 52: r eceive stm-0/stm-1 t ransport s tatus r egister 1 (rtsr1 = 0 x 0206) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused section trace message (j0) mismatch defect declared section trace message (j0) unstable defect declared ais-l defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 122 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - rdi-l defect declared indicator this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is detecting t he rdi-l (line-remote defect indicator) defect condition, wi thin the incoming stm-0 signal. the receive stm-0 toh processor block will declare the rdi-l defect condition whene ver bits 6, 7 and 8 (e.g., the three least signific ant bits) of the k2 byte contains the 1, 1, 0 pattern in 5 consecutive incom ing stm-0 frames. 0 - indicates that the rdi-l defect condition is no t currently being declared. 1 - indicates that the rdi-l defect condition is cu rrently being declared. bit 6 - s1 byte unstable defect declared this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the s1 byte unstable defect condition. the receive stm -0 toh processor block will declare the s1 byte uns table defect condition whenever the s1 byte unstable counter rea ches the value 32. the s1 byte unstable counter is incremented for each time that the receive stm-0 toh processor block receives an stm-0 frame that contains an s1 b yte that differs from the previously received s1 byte. the s1 byte unstable counter is cleared to 0 when the s ame s1 byte is received for 8 consecutive stm-0 frames. n ote : receiving a given s1 byte, in 8 consecutive stm-0 f rames also sets this bit-field to 0. 0 - indicates that the s1 byte unstable defect cond ition is not currently being declared. 1 - indicates that the s1 byte unstable defect cond ition is currently being declared. bit 5 - k1, k2 byte unstable defect declared this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the k1, k2 byte unstable defect condition. the receive stm-0 toh processor block will declare the k1, k2 byte unstable defect condition whenever the receive stm-0 toh pro cessor block fails to receive the same set of k1, k 2 bytes, in 12 consecutive incoming stm-0 frames. the k1, k2 byt e unstable defect condition is cleared whenever the receive stm-0 toh processor block has received a given set of k1, k2 byte values within three consecutive inco ming stm-0 frames. 0 - indicates that the k1, k2 byte unstable defect condition is not currently being declared. 1 - indicates that the k1, k2 byte unstabel defect condition is currently being declared. bit 4 - sf (signal failure) defect declared this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the sf defect condition. the receive stm-0 toh process or block will declare the sf defect condition anyti me it has determined that the number of b2 byte errors (measu red over a user-selected period of time) exceeds a certain user- specified b2 byte error threshold. 0 - indicates that the sf defect condition is not c urrently being declared. this bit is set to 0 when the number of b2 byte err ors (accumulated over a given interval of time) doe s not exceed the sf defect declaration threshold. 1 - indicates that the sf defect condition is curre ntly being declared. this bit is set to 1 when the number of b2 errors ( accumulated over a given interval of time) does exc eed the sf defect declaration threshold. bit 3 - sd (signal degrade) defect declared this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the sd defect condition. the receive stm-0 toh process or block will declare the sd defect condition anyti me it has t able 53: r eceive stm-0/stm-1 t ransport s tatus r egister 0 (rtsr0 = 0 x 0207) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdi-l defect declared s1 byte unstable defect declared k1, k2 byte unstable defect declared sf defect declared sd defect declared lofdefect detected sefdefect declared losdefect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 123 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 determined that the number of b2 byte errors (measu red over a user-selected period of time) exceeds a certain user- specified b2 byte error threshold. 0 - indicates that the sd defect condition is not c urrently being declared. this bit is set to 0 when the number of b2 errors ( accumulated over a given interval of time) does not exceed the sd declaration threshold. 1 - indicates that the sd defect condition is curre ntly being declared.this bit is set to 1 when the n umber of b2 errors (accumulated over a given interval of time) does ex ceed the sd defect declaration threshold. bit 2 - lof (loss of frame) defect declared this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the lof defect condition. the receive stm-0 toh proces sor block will declare the lof defect condition if it has been declaring the sef condition for 24 consecutive stm- 0 frame periods. once the lof defect is declared, then the receive stm-0 toh processor block will clear the lo f defect if it has not been declaring the sef condi tion for 3ms (or 24 consecutive stm-0 frame periods). 0 - indicates that the receive stm-0 toh processor block is not currently declaring the lof defect con dition. 1 - indicates that the receive stm-0 toh processor block is currently declaring the lof defect conditi on. bit 1 - sef (severely errored frame) defect declare d this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the sef defect condition. the receive stm-0 toh proces sor block will declare the sef defect condition if it detects framing alignment byte errors in four consecutive s tm-0 frames. once the receive toh processor block declares the sef defect condition, the receive stm-0 toh pro cessor block will then clear the sef defect conditi on if it detects two consecutive stm-0 frames with un-erred framing alignment bytes. if the receive toh processor bloc k declares the sef defect condition for 24 consecutive stm-0 f rame periods, then it will declare the lof defect c ondition. 0 - indicates that the receive stm-0 toh processor block is not currently declaring the sef defect con dition. 1 - indicates that the receive stm-0 toh processor block is currently declaring the sef defect conditi on. bit 0 - los (loss of signal) defect declared this read-only bit-field indicates whether or not t he receive stm-0 toh processor block is currently d eclaring the los (loss of signal) defect condition. the receive stm-0 toh processor block will declare the los def ect condition if it detects los_threshold[15:0] consecutive all z ero bytes in the incoming stm-0 data stream. n ote : the user can set the los_threshold[15:0] value by w riting the appropriate data into the receive stm-0 transport - los threshold value register (address l ocation= 0x022e and 0x022f). 0 - indicates that the receive stm-0 toh processor block is not currently declaring the los defect con dition. 1 - indicates that the receive stm-0 toh processor block is currently declaring the los defect conditi on.
preliminary XRT86SH221 124 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7: 2] - unused bit 1 - change of ais-l (line ais) defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change of ais-l defect condition interrupt has occurred since the last read of this register. the receive stm-0 toh processor block will generate this interr upt in response to either of the following occurrences. whenever the receive stm-0 toh processor block declares the ais -l defect condition. whenever the receive stm-0 toh process or block clears the ais-l defect condition. 0 - indicates that the change of ais-l defect condi tion interrupt has not occurred since the last read of this register. 1 - indicates that the change of ais-l defect condi tion interrupt has occurred since the last read of this register. n ote : the user can obtain the current state of the ais-l defect condition by reading the contents of bit 0 ( ais-l defect declared) within the receive stm-0 transport status register - byte 1 (address location= 0x0206 ). bit 0 - change of rdi-l (line - remote defect indic ator) defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change of rdi-l defect condition interrupt has occurred since the last read of this register. the receive stm-0 toh processor block will generate this interr upt in response to either of the following occurrences. ? whenever the receive stm-0 toh processor block decl ares the rdi-l defect condition. ? whenever the receive stm-0 toh processor block clea rs the rdi-l defect condition. 0 - indicates that the change of rdi-l defect condi tion interrupt has not occurred since the last read of this register. 1 - indicates that the change of rdi-l defect condi tion interrupt has occurred since the last read of this register.note: n ote : the user can obtain the current state of the rdi-l defect condition by reading out the state of bit7 ( rdi-l defect declared) within the receive stm-0 transport status register - byte 0 (address location= 0x0207 ). t able 54: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 2 (rtisr2 = 0 x 0209) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused change of ais-ldefect condition interrupt status change of rdi-l defect condition interrupt status r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 125 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - new s1 byte value interrupt status this reset-upon-read bit-field indicates whether or not the new s1 byte value interrupt has occurred s ince the last read of this register. the receive stm-0 toh proce ssor block will generate the new s1 byte value inte rrupt, anytime it has accepted a new s1 byte, from the incoming st m-0 data-stream. 0 - indicates that the new s1 byte value interrupt has not occurred since the last read of this regist er. 1 - indicates that the new s1 byte value interrupt has occurred since the last read of this register. n ote : the user can obtain the value for this most recentl y accepted value of the s1 byte by reading the rece ive stm- 0 transport s1 byte value register (address locatio n= 0x0227). bit 6 - change in s1 byte unstable defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in s1 byte unstable defect conditio n interrupt has occurred since the last read of this register. the receive stm-0 toh processor block will generat e this interrupt in response to either of the following events. ? whenever the receive stm-0 toh processor block decl ares the s1 byte unstable defect condition. ? whenever the receive stm-0 toh processor block clea rs the s1 byte unstable defect condition. 0 - indicates that the change in s1 byte unstable d efect condition interrupt has occurred since the la st read of this register. 1 - indicates that the change in s1 byte unstable d efect condition interrupt has not occurred since th e last read of this register. n ote : the user can obtain the current s1 byte unstable de fect condition by reading the contents of bit6 (s1 byte unstable defect declared) within the receive stm-0 transport status register - byte 0 (address locatio n= 0x0207). bit 5 - change in section trace message unstable de fect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in section trace message unstable d efect condition interrupt has occurred since the last rea d of this register. the receive stm-0 toh processo r block will generate this interrupt in response to either of th e following events. ? whenever the receive stm-0 toh processor block decl ares the section trace message unstable defect condition. ? whenever the receive stm-0 toh processor block clea r the section trace message unstable defect condition. indicates that the change in section trace message unstable defect condition interrupt has not occurre d since the last read of this register. 1 - indicates that the change in section trace mess age unstable defect condition interrupt has occurre d since the last read of this register. bit 4 - new section trace message interrupt status this reset-upon-read bit-field indicates whether or not the new section trace message interrupt has oc curred since the last read of this register. the receive stm-0 toh processor block will generate this interrupt an ytime it has accepted a new section trace message within the inc oming stm-0 data-stream. t able 55: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 1 (rtisr1 = 0 x 020a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new s1 byteinter- rupt status change in s1 byte unstablede- fect condi- tioninterrupt status change in section trace mes- sage unsta- ble defect condition interrupt sta- tus new section trace mes- sage inter- rupt status change in section trace mes- sage mis- matchdefect declared interrupt sta- tus unused change in k1, k2 byte unstable defect cond- tion interrupt status new k1k2 byte value interrupt sta- tus rur rur rur rur rur r/o rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 126 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 0 - indicates that the new section trace message in terrupt has not occurred since the last read of thi s register. 1 - indicates that the new section trace message in terrupt has occurred since the last read of this re gister. n ote : the user can read out the contents of the receive s ection trace message buffer, which is located at ad dress locations 0x0400 through 0x04ff). bit 3 - change in section trace message mismatch de fect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in section trace mismatch defect co ndition interrupt has occurred since the last read of this register. the receive stm-0 toh processor block wi ll generate this interrupt in response to either of the following ev ents. whenever the receive stm-0 toh processor bl ock declares the section trace message mismatch defect condition whenever the receive stm-0 toh processor block c lears the section trace mismatch defect condition. 0 - indicates that the change in section trace mess age mismatch defect condition interrupt has not occ urred since the last read of this register. 1 - indicates that the change in section trace mess age mismatch defect condition interrupt has occurre d since the last read of this register. n ote : the user can determine whether the section trace me ssage mismatch condition is currently cleared or declared by reading the state of bit 2 (section tra ce message mismatch defect declared) within the rec eive stm-0 transport status register - byte 1 (address l ocation= 0x0206). bit 2 - unused bit 1 - change in k1, k2 byte unstable defect condi tion interrupt status this reset-upon-read bit-field indicates whether or not the change in k1, k2 byte unstable defect cond ition interrupt has occurred since the last read of this register. the receive stm-0 toh processor block wi ll generate this interrupt in response to either of the following ev ents. ? whenever the receive stm-0 toh processor block dec lares the k1, k2 byte unstable defect condition. ? whenever the receive stm-0 toh processor block clea rs the k1, k2 byte unstable defect condition. 0 - indicates that the change of k1, k2 byte unstab le defect condition interrupt has not occurred sinc e the last read of this register. 1 - indicates that the change of k1, k2 byte unstab le defect condition interrupt has occurred since th e last read of this register. n ote : the user can determine whether the k1, k2 byte unst able defect condition is currently being declared o r cleared by reading out the contents of bit 5 (k1, k 2 byte unstable defect declared), within the receiv e stm- 0 transport status register - byte 0 (address locat ion= 0x0207). bit 0 - new k1, k2 byte value interrupt status this reset-upon-read bit-field indicates whether or not the new k1, k2 byte value interrupt has occurr ed since the last read of this register. the receive stm-0 toh processor block will generate this interrupt whenev er its has accepted a new set of k1, k2 byte values from the i ncoming stm-0 data-stream 0 - indicates that the new k1, k2 byte value interr upt has not occurred since the last read of this re gister. 1 - indicates that the new k1, k2 byte value interr upt has occurred since the last read of this regist er. n ote : the user can obtain the contents of the new k1 byte by reading out the contents of the receive stm-0 transport k1 byte value register (address location= 0xn11f). further, the user can also obtain the co ntents of the new k2 byte by reading out the contents of t he receive stm-0 transport k2 byte value register (address location= 0x0223).
XRT86SH221 preliminary 127 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - change of signal failure (sf) defect condit ion interrupt status this reset-upon-read bit-field indicates whether or not the change of sf defect condition interrupt ha s occurred since the last read of this register. the receive stm-0 toh processor block will generate this interr upt in response to either of the following events. ? whenever the receive stm-0 toh processor block dec lares the sf defect condition. ? whenever the receive stm-0 toh processor block clea rs the sf defect condition. 0 - indicates that the change of sf defect conditio n interrupt has not occurred since the last read of this register. 1 - indicates that the change of sf defect conditio n interrupt has occurred since the last read of thi s register. n ote : the user can determine whether or not the sf defect condition is currently being declared by reading o ut the state of bit 4( sf defect declared) within the rece ive stm-0 transport status register - byte 0 (addre ss location= 0x0207). bit 6 - change of signal degrade (sd) defect condit ion interrupt status this reset-upon-read bit-field indicates whether or not the change of sd defect condition interrupt ha s occurred since the last read of this register. the receive stm-0 toh processor block will generate this interr upt in response to either of the following events. ? whenver the receive stm-0 toh processor block decl ares the sd defect condition. ? whenever the receive stm-0 toh processor block clea rs the sd defect condition. 0 - indicates that the change of sd defect conditio n interrupt has not occurred since the last read of this register. 1 - indicates that the change of sd defect conditio n interrupt has occurred since the last read of thi s register. n ote : the user can determine whether or not the sd defect condition is currently being declareds by reading out the state of bit 3 (sd defect declared) within the rece ive stm-0 transport status register - byte 0 (addre ss location= 0x0207). bit 5 - detection of rei-l (line - remote error ind icator) event interrupt status this reset-upon-read bit-field indicates whether or not the detection of rei-l event interrupt has occ urred since the last read of this register. the receive stm-0 toh processor block will generate this interrupt anytim e it detects an rei-l event within the incoming stm-0 data-stream. 0 - indicates that the detection of rei-l event int errupt has not occurred since the last read of this register. 1 - indicates that the detection of rei-l event int errupt has occurred since the last read of this reg ister. bit 4 - detection of b2 byte error interrupt status this reset-upon-read bit-field indicates whether or not the detection of b2 byte error interrupt has o ccurred since the last read of this register. the receive stm-0 toh processor block will generate this interrupt an ytime it detects a b2 byte error within the incoming stm-0 data-stream . 0 - indicates that the detection of b2 byte error i nterrupt has not occurred since the last read of th is register. 1 - indicates that the detection of b2 byte error i nterrupt has occurred since the last read of this r egister. bit 3 = detection of b1 byte error interrupt status this reset-upon-read bit-field indicates whether or not the detection of b1 byte error interrupt has o ccurred since the last read of this register. the receive stm-0 toh processor block will generate this interrupt an ytime it detects a b1 byte error within the incoming stm-0 data-stream . t able 56: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 0 (rtisr0 = 0 x 020b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of sf defect conditionin- terrupt sta- tus change of sd defect condition interrupt sta- tus detection of rei-l event error inter- rupt status detection of b2 byte error inter- rupt status detection of b1 byte error inter- rupt status change of lof defect condition interrupt sta- tus change of sef defect interrupt sta- tus change of los defect condition interrupt sta- tus rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 128 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 0 - indicates that the detection of b1 byte error i nterrupt has not occurred since the last read of th is register. 1 - indicates that the detection of b1 byte error i nterrupt has occurred since the last read of this r egister bit 2 - change of loss of frame (lof) defect condit ion interrupt status this reset-upon-read bit-field indicates whether or not the change of lof defect condition interrupt h as occurred since the last read of this register. the receive stm-0 toh processor block will generate this interr upt in response to either of the following events. ? whenever the receive stm-0 toh processor block dec lares the lof defect condition. ? whenever the receive stm-0 toh processor block clea rs the lof defect condition. 0 - indicates that the change of lof defect conditi on interrupt has not occurred since the last read o f this register. 1 - indicates that the change of lof defect conditi on interrupt has occurred since the last read of th is register. n ote : the user can determine whether or not the receive s tm-0 toh processor block is currently declaring the lof defect condition by reading out the state of bit 2 (lof defect declared) within the receive stm-0 tran sport status register - byte 0 (address location= 0x0207) . bit 1 - change of sef defect condition interrupt st atus this reset-upon-read bit-field indicates whether or not the change of sef defect condition interrupt h as occurred since the last read of this register. the receive stm-0 toh processor block will generate this interr upt in response to either of the following events. ? whenever the receive stm-0 toh processor block decl ares the sef defect condition. ? whenever the receive stm-0 toh processor block clea rs the sef defect condition. 0 - indicates that the change of sef defect conditi on interrupt has not occurred since the last read o f this register. 1 - indicates that the change of sef defect conditi on interrupt has occurred since the last read of th is register. n ote : the user can determine whether or not the receive s tm-0 toh processor block is currently declaring the sef defect condition by reading out the state of bit 1 (sef defect declared) within the receive stm-0 tran sport status register - byte 0 (address location= 0x0207) . bit 0 - change of loss of signal (los) defect condi tion interrupt status this reset-upon-read bit-field indicates whether or not the change of los defect condition interrupt h as occurred since the last read of this register. the receive stm-0 toh processor block will generate this interr upt in response to either of the following events. ? whenever the receive stm-0 toh processor block decl ares the los defect condition. ? whenever the receive stm-0 toh processor block cle ars the los defect condition. 0 - indicates that the change of los defect conditi on interrupt has not occurred since the last read o f this register. 1 - indicates that the change of los defect conditi on interrupt has occurred since the last read of th is register. n ote : the user can determine whether or not the receive s tm-0 toh processor block is currently declaring the los defect condition by reading out the contents of bit 0 (los defect declared) within the receive stm-0 transport status register - byte 0 (address locatio n= 0x0207).
XRT86SH221 preliminary 129 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:2] - unused bit 1- change of ais-l (line ais) defect condition interrupt enable this read/write bit-field is used to either enable or disable the change of ais-l defect condition int errupt. if this interrupt is enabled, then the xrt86sh328 will gene rate an interrupt in response to either of the foll owing conditions. ? when the receive stm-0 toh processor block declares the ais-l defect condition. ? when the receive stm-0 toh processor block clears t he ais-l defect condition. 0 - disables the change of ais-l defect condition i nterrupt. 1 - enables the change of ais-l defect condition in terrupt. bit 0 - change of rdi-l (line remote defect indicat or) defect condition interrupt enable this read/write bit-field is used to either enable or disable the change of rdi-l defect condition int errupt. if this interrupt is enabled, then the xrt86sh328 will gene rate an interrupt in response to either of the foll owing conditions. when the receive stm-0 toh processor block declares the rdi-l defect condition. when the receive stm -0 toh processor block clears the rdi-l defect condition. 0 - disables the change of rdi-l defect condition i nterrupt. 1 - enables the change of rdi-l defect condition in terrupt. t able 57: r eceive stm-0/stm-1 t ransport i nterrupt e nable r egister 2 (rtier2 = 0 x 020d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused change of ais-ldefect condition interrupt enable change of rdi-ldefect condition interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 130 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - new s1 byte value interrupt enable this read/write bit-field is used to enable or disa ble the new s1 byte value interrupt. if this interrupt is enabled, then the receive stm- 0 toh processor block will generate this interrupt anytime it receives and accepts a new s1 byte value. the receive stm-0 toh processor block will accept a new s1 byte afte r it has received it for 8 consecutive stm-0 frames. 0 - disables the new s1 byte value interrupt. 1 - enables the new s1 byte value interrupt. bit 6 - change in s1 byte unstable defect condition interrupt enable this read/write bit-field is used to either enable or disable the change in s1 byte unstable defect co ndition interrupt.. if the user enables this bit-field, then the receiv e stm-0 toh processor block will generate an interr upt in response to either of the following conditions ? when the receive stm-0 toh processor block declares the s1 byte unstable defect condition ? when the receive stm-0 toh processor block clears t he s1 byte unstable defect condition. 0 - disables the change in s1 byte unstable defect condition interrupt. 1 - enables the change in s1 byte unstable defect c ondition interrupt. bit 5 - change in section trace message unstable de fect condition interrupt enable this read/write bit-field is used to either enable or disable the change in section trace message unst able defect condition interrupt. if this interrupt is enabled, then the receive stm- 0 toh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive stm-0 toh processor block decl ares the section trace message unstable defect condition. ? whenever the receive stm-0 toh processor block clea rs the section trace message unstable defect condition. 0 - disable the change of section trace message uns table defect condition interrupt. 1 - enables the change of section trace message uns table defect condition interrupt. bit 4 - new section trace message interrupt enable this read/write bit-field is used to enable or disa ble the new section trace message interrupt. if this interrupt is enabled, then the receive stm- 0 toh processor block will generate this interrupt anytime it receives and accepts a new section trace message within the incoming stm-0 data-stream. the receive stm-0 toh processor block will accept a new section trace mes sage after it has received it 3 (or 5) consecutive times. 0 - disables the new section trace message interrup t. 1 - enables the new section trace message interrupt . t able 58: r eceive stm-0/stm-1 t ransport i nterrupt e nable r egister 1 (rtier1 = 0 x 020e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new s1 byte interrupt enable change in s1 byte unstable defect con- ditioninter- rupt enable change in section trace mes- sage unsta- ble defect condition interrupt enable new section trace mes- sage inter- rupt enable change in section trace mes- sage mis- match defect condition interrupt enable unused change in k1, k2 byte unstable defect con- ditioninter- rupt enable new k1k2 byte value interrupt enable r/w r/w r/w r/w r/w r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 131 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 3 - change in section trace mismatch defect con dition interrupt enable: this read/write bit-field is used to either enable or disable the change in section trace mismatch def ect condition interrupt. if this interrupt is enabled, then the receive stm -0 toh processor block will generate an interrupt i n response to either of the following events. ? whenever the receive stm-0 toh processor block dec lares the section trace message mismatch defect condition. ? whenever the receive stm-0 toh processor block clea rs the section trace message mismatch defect condition. n ote : the user can determine whether or not the receive s tm-0 toh processor block is currently declaring the section trace message mismatch defect condition by reading the state of bit 2 (section trace message mismatch defect condition declared) within the rece ive stm-0 transport status register - byte 1 (addre ss location= 0x0206). bit 2 - unused bit 1 - change of k1, k2 byte unstable defect condi tion - interrupt enable this read/write bit-field is used to either enable or disable the change of k1, k2 byte unstable defec t condition interrupt. if this interrupt is enabled, then the receive stm-0 toh processor block will generate an interrupt in response to either of the following events.a.whenev er the receive stm-0 toh processor block declares t he k1, k2 byte unstable defect condition. b.whenever the rece ive stm-0 toh processor block clears the k1, k2 byt e unstable defect condition. 0 - disables the change of k1, k2 byte unstable def ect condition interrupt. 1 - enables the change of k1, k2 byte unstable defe ct condition interrupt. bit 0 - new k1, k2 byte value interrupt enable this read/write bit-field is used to either enable or disable the new k1, k2 byte value interrupt. if this interrupt is enabled, then the receive stm-0 toh processor block will generate this interrupt anytime it receives a nd accepts a new k1, k2 byte value. the receive stm-0 toh proce ssor block will accept a new k1, k2 byte value, aft er it has received it within 3 (or 5) consecutive stm-0 frame s. 0 - disables the new k1, k2 byte value interrupt. 1 - enables the new k1, k2 byte value interrupt.
preliminary XRT86SH221 132 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - change of signal failure (sf) defect condit ion interrupt enable this read/write bit-field is used to either enable or disable the change of signal failure (sf) defect condition interrupt. if this interrupt is enabled, then the xrt86sh328 will generate an interrupt in response t o any of the following events. ? whenever the receive stm-0 toh processor block dec lares the sf defect condition. ? whenever the receive stm-0 toh processor block clea rs the sf defect condition. 0 - disables the change of sf defect condition inte rrupt. 1 - enables the change of sf defect condition inter rupt. bit 6 - change of signal degrade (sd) defect condit ion interrupt enable this read/write bit-field is used to either enable or disable the change of signal degrade (sd) defect condition interrupt. if this interrupt is enabled, then the xrt86sh328 will generate an interrupt in response t o either of the following events. ? whenever the receive stm-0 toh processor blolck de clares the sd defect condition. ? whenever the receive stm-0 toh processor block cle ars the sd defect condition. 0 - disables the change of sd defect condition inte rrupt. 1 - enables the change of sd defect condition inter rupt. bit 5 - detection of rei-l (line - remote error ind icator) event interrupt enable this read/write bit-field is used to either enable or disable the detection of rei-l event interrupt. if this interrupt is enabled, then the xrt86sh328 will generate an inter rupt anytime the receive stm-0 toh processor block detects an rei-l condition within the incoming stm-0 data-stre am. 0 - disables the detection of rei-l event interrupt . 1 - enables the detection of rei-l event interrupt. bit 4 - detection of b2 byte error interrupt enable this read/write bit-field is used to either enable or disable the detection of b2 byte error interrupt . if this interrupt is enabled, then the xrt86sh328 will generate an in terrupt anytime the receive stm-0 toh processor blo ck detects a b2 byte error within the incoming stm-0 data-stre am. 0 - disables the detection of b2 byte error interru pt. 1 - enables the detection of b2 byte error interrup t. bit 3 - detection of b1 byte error interrupt enable : this read/write bit-field is used to either enable or disable the detection of b1 byte error interrupt . if this interrupt is enabled, then the xrt86sh328 will generate an in terrupt anytime the receive stm-0 toh processor blo ck detects a b1 byte error within the incoming stm-0 data-stre am. 0 - disables the detection of b1 byte error interru pt. 1 - enables the detection of b1 byte error interrup t. bit 2 - change of loss of frame (lof) defect condit ion interrupt enable this read/write bit-field is used to either enable or disable the change of lof defect condition inter rupt. if this interrupt is enabled, then the xrt86sh328 will gene rate an interrupt in response to either of the foll owing conditions t able 59: r eceive stm-0/stm-1 t ransport i nterrupt s tatus r egister 0 (rtier0 = 0 x 020f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of sf defect- condition interrupt enable change of sd defect condition interrupt enable detection of rei-l event interrupt enable detection of b2 byte error inter- rupt enable detection of b1 byte error inter- rupt enable change of lof defect condition interrupt enable change of sef defect condition interrupt enable change of los defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 133 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 ? when the receive stm-0 toh processor block declares the lof defect condition ? when the receive stm-0 toh processor block clears the lof defect condition. 0 - disables the change of lof defect condition int errupt. 1 - enables the change of lof defect condition inte rrupt. bit 1 - change of sef defect condition interrupt en able this read/write bit-field is used to either enable or disable the change of sef defect condition inter rupt. if this interrupt is enabled, then the xrt86sh328 will gene rate an interrupt in response to either of the foll owing conditions. ? when the receive stm-0 toh processor block declares the sef defect condition. ? when the receive stm-0 toh processor block clears the sef defect condition. 0 - disables the change of sef defect condition in terrupt. 1 - enables the change of sef defect condition inte rrupt. bit 0 - change of loss of signal (los) defect condi tion interrupt enable this read/write bit-field is used to either enable or disable the change of lof defect condition inter rupt. if this interrupt is enabled, then the xrt86sh328 will gene rate an interrupt in response to either of the foll owing conditions. ? when the receive stm-0 toh processor block declares the lof defect condition. ? when the receive stm-0 toh processor block clears t he lof defect condition. 0 - disables the change of lof defect condition int errupt. 1 - enables the change of lof defect condition inte rrupt. bit [7:0] - b1 byte error count - msb this reset-upon-read register, along with receive s tm-0 transport - b1 byte error count register - byt es 2 through 0, function as a 32 bit counter, which is i ncremented anytime the receive stm-0 toh processor block detects a b1 byte error. n otes : 1. if the receive stm-0 toh processor block is confi gured to count b1 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming stm- 0 frame) that are in error 2. if the receive stm-0 toh processor block is confi gured to count b1 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains an erred b1 byte. t able 60: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 3 (b1becr3 = 0 x 0210) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 134 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - b1 byte error count (bits 23 through 16) this reset-upon-read register, along with receive s tm-0 transport - b1 byte error count register - byt es 3, 1 and 0, function as a 32 bit counter, which is increment ed anytime the receive stm-0 toh processor block de tects a b1 byte error. n otes : 1. if the receive stm-0 toh processor block is confi gured to count b1 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming stm- 0 frame) that are in error. 2. if the receive stm-0 toh processor block is conf igured to count b1 byte errors on a per-frame basis , then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains an erred b1 byte. bit [7:0] - b1 byte error count - (bits 15 through 8) this reset-upon-read register, along with receive s tm-0 transport - b1 byte error count register - byt es 3, 2 and 0, function as a 32 bit counter, which is increment ed anytime the receive stm-0 toh processor block de tects a b1 byte error. n otes : 1. if the receive stm-0 toh processor block is confi gured to count b1 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming stm- 0 frame) that are in error 2. if the receive stm-0 toh processor block is confi gured to count b1 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains an erred b1 byte. t able 61: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 2 (b1becr2 = 0 x 0211) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 62: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 1 (b1becr1 = 0 x 0212) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 135 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - b1 byte error count - lsb this reset-upon-read register, along with receive s tm-0 transport - b1 byte error count register - byt es 3 through 1, function as a 32 bit counter, which is i ncremented anytime the receive stm-0 toh processor block detects a b1 byte error. n otes : 1. if the receive stm-0 toh processor block is confi gured to count b1 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming stm- 0 frame) that are in error. 2. if the receive stm-0 toh processor block is confi gured to count b1 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains an erred b1 byte. bit [7:0] - b2 byte error count - msb this reset-upon-read register, along with receive s tm-0 transport - b2 byte error count register - byt es 2 through 0, function as a 32 bit counter, which is i ncremented anytime the receive stm-0 toh processor block detects a b2 byte error. n otes : 1. if the receive stm-0 toh processor block is confi gured to count b2 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b2 byte (of each incoming stm- 0 frame) that are in error. 2. if the receive stm-0 toh processor block is confi gured to count b2 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains an erred b2 byte. t able 63: r eceive stm-0/stm-1 t ransport - b1 b yte e rror c ount r egister 0 (b1becr0 = 0 x 0213) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 64: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 3 (b2becr3= 0 x 0214) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 136 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - b2 byte error count (bits 23 through 16 ) this reset-upon-read register, along with receive t ransport - b2 byte error count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 toh processor block detec ts a b2 byte error. n otes : 1. if the receive stm-0 toh processor block is confi gured to count b2 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b2 byte (of each incoming stm- 0 frame) that are in error. 2. if the receive stm-0 toh processor block is confi gured to count b2 byte errors on a per-bit basis, t hen it will increment this 32 bit counter each time tha t it receives an stm-0 frame that contains an erred b2 byte. bit [7:0] - b2 byte error count - (bits 15 through 8) this reset-upon-read register, along with receive t ransport - b2 byte error count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 toh processor block detec ts a b2 byte error. n otes : 1. if the receive stm-0 toh processror block is conf igured to count b2 byte errors on a per-bit basis, then it will increment this 32 bit counter by the number of bits, within the b2 byte (of each incoming stm- 0 frame) that are in error. 2. if the receive stm-0 toh processor block is confi gured to count b2 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains an erred b2 byte. t able 65: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 2 (b2becr2 = 0 x 0215) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 66: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 1 (b2becr1 = 0 x 0216) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 137 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - b2 byte error count - lsb this reset-upon-read register, along with receive t ransport - b2 byte error count register - bytes 3 t hrough 1, function as a 32 bit counter, which is incremented anytime the receive stm-0 toh processor block detec ts a b2 byte error. n otes : 1. if the receive stm-0 toh processor block is confi gured to count b2 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b2 byte (of each incoming stm- 0 frame) that are in error. 2. if the receive stm-0 toh processor block is conf igured to count b2 byte errors on a per-frame basis , then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains an erred b2 byte. bit [7:0] - rei-l event count - msb this reset-upon-read register, along with receive s tm-0 transport - rei-l event count register - bytes 2 through 0, function as a 32 bit counter, which is increment ed anytime the receive stm-0 toh processor block de tects a line - remote error indicator event within the incoming stm-0 data-stream. n otes : 1. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-va lue within the rei-l field of the m0 byte within ea ch incoming stm-0 frame. 2. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains a n on-zero rei-l value. t able 67: r eceive stm-0/stm-1 t ransport - b2 b yte e rror c ount r egister 0 (b2becr0 = 0 x 0217) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 68: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 3 (reilecr3 = 0 x 0218) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 138 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - rei-l event count (bits 23 through 16) this reset-upon-read register, along with receive s tm-0 transport - rei-l event count register - bytes 3, 1 and 0, function as a 32 bit counter, which is increment ed anytime the receive stm-0 toh processor block de tects a line - remote error indicator event within the incoming stm-0 data-stream. n otes : 1. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-va lue within the rei-l field of the m0 byte within ea ch incoming stm-0 frame. 2. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains a n on-zero rei-l value. bit [7:0] - rei-l event count - (bits 15 through 8) this reset-upon-read register, along with receive s tm-0 transport - rei-l event count register - bytes 3, 2 and 0, function as a 32 bit counter, which is increment ed anytime the receive stm-0 toh processor block de tects a line -remote error indicator event within the incoming s tm-0 data-stream. n otes : 1. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-va lue within the rei-l field of the m0 byte within ea ch incoming stm-0 frame. 2. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains a n on-zero rei-l value. t able 69: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 2 (reilecr2 = 0 x 0219) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 70: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 1 (reilecr1 = 0 x 021a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 139 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - rei-l event count - lsb this reset-upon-read register, along with receive s tm-0 transport - rei-l event count register - bytes 3 through 1, function as a 32 bit counter, which is increment ed anytime the receive stm-0 toh processor block de tects a line - remote error indicator event within the incoming stm-0 data-stream. n otes : 1. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-va lue within the rei-l field of the m0 byte. 2. if the receive stm-0 toh processor block is confi gured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 frame that contains a n on-zero rei-l value. bit [7:0]filtered/accepted k1 byte value these read-only bit-fields contain the value of the most recently filtered k1 byte value that the rece ive stm-0 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive stm-0 frames. this register should be polled by software in order to determine various aps codes. bit [7:0]filtered/accepted k2 byte value these read-only bit-fields contain the value of the most recently filtered k2 byte value that the rece ive stm-0 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive stm-0 frames. this register should be polled by software in order to determine various aps codes. t able 71: r eceive stm-0/stm-1 t ransport - rei-l e vent c ount r egister 0 (reilecr0 = 0 x 021b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 72: r eceive stm-0/stm-1 t ransport - r eceived k1 b yte v alue r egister (rk1bvr = 0 x 021f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filtered_k1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 73: r eceive stm-0/stm-1 t ransport - r eceived k2 b yte v alue r egister (rk2bvr = 0 x 0223) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filtered_k2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 140 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - filtered/accepted s1 byte value these read-only bit-fields contain the value of the most recently filtered s1 byte value that the rece ive stm-0 toh processor block has received. these bit-fields are valid if it has been received for 8 consecutive st m-0 frames. bit [7:5] - unused bit [4:3] - frpatout[1:0] these bits allow software to select from 3 differen t framing algorithms when the framer is trying to d etect sef (oof). 00, 01 - 16-bits (last a1 byte + first a2 byte) 10 - 32-bits (last two a1 bytes + first two a2 byte s) 11 - 48-bits (last three a1 bytes + first three a2 bytes) bit [2:1] - frpatin[1:0] these bits allow software to specify the algorithm used to check for frame alignment patterns (a1/a2). 00, 01 - 16-bits (last a1 byte + first a2 byte) 10 - 32-bits (last two a1 bytes + first two a2 byte s) 11 - 48-bits (last three a1 bytes + first three a2 bytes) bit 0 - unused bit [7:0] - los threshold value - msb these read/write bits, along the contents of the re ceive stm-0/stm-1 transport - los threshold value - lsb register is used specify the number of consecutive (all zero) bytes that the receive stm-0/stm-1 toh p rocessor block must detect (within the incoming stm-0/stm-1 data-s tream) before it can declare the los defect conditi on. n ote : this register contains the msb (most significant by te) of this 16-bit expression. t able 74: r eceive stm-0/stm-1 t ransport - r eceived s1 b yte v alue r egister (rs1bvr = 0 x 0227) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filtered_s1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 75: r eceive stm-0/stm-1 t ransport - r eceive i n -s ync t hreshold r egister (ristr = 0 x 022b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused frpatout[1:0] frpatin[1:0] unused r/o r/o r/o r/w r/w r/w r/w r/o 0 0 0 0 0 0 0 0 t able 76: r eceive stm-0/stm-1 t ransport - los t hreshold v alue 1 (lostv1 = 0 x 022e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 los_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH221 preliminary 141 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - los threshold value - lsb these read/write bits, along the contents of the re ceive stm-0/stm-1 transport - los threshold value - msb register is used to specify the number of consecuti ve (all zero) bytes that the receive stm-0/stm-1 to h processor block must detect (within the incoming stm-0/stm-1 data-stream) before it can declare the los defect c ondition. n ote : this register contains the lsb (least significant b yte) of this 16-bit expression. bit [7:0] - sf_set_monitor_interval - msb these read/write bits, along the contents of the re ceive stm-0/stm-1 transport - sf set monitor interv al - byte 1 and byte 0 registers are used to specify the leng th of the monitoring period (in terms of ms) for sf (signal failure) defect declaration. when the receive stm-0/stm-1 toh processor block is checking the incoming stm-0/stm-1 signal in order to determine if it should declare the sf defect condit ion, it will accumulate b2 byte errors throughout t he user-specified sf defect declaration monitoring period. if, during t his sf defect declaration monitoring period, the re ceive stm-0/stm- 1 toh processor block accumulates more b2 byte erro rs than that specified within the receive transport sf set threshold register, then the receive stm-0/stm-1 to h processor block will declare the sf defect condit ion. n otes : 1. the value that the user writes into these three ( 3) sf set monitor window registers, specifies the duration of the sf defect declaration monitoring pe riod, in terms of ms. 2. this particular register byte contains the msb (m ost significant byte) value of the three registers that specify the sf defect declaration monitoring period . bit [7:0] - sf_set_monitor_interval (bits 15 throug h 8) these read/write bits, along the contents of the re ceive stm-0/stm-1 transport - sf set monitor interv al - byte 2 and byte 0 registers are used to specify the leng th of the monitoring period (in terms of ms) for sf (signal failure) defect declaration. when the receive stm-0/stm-1 toh processor block is checking the incoming stm-0/stm-1 signal in order to determine if it should declare the sf defect condit ion, it will accumulate b2 byte errors throughout t he user-specified sf defect declaration monitoring period. if, during t his sf defect declaration monitoring period the rec eive stm-0/stm- 1 toh processor block accumulate more b2 byte error s than that specified within the receive stm-0/stm- 1 transport t able 77: r eceive stm-0/stm-1 t ransport - los t hreshold v alue 0 (lostv0 = 0 x 022f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 los_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 78: r eceive stm-0/stm-1 t ransport - r eceive sf set m onitor i nterval 2 (rsfsmi2= 0 x 0231) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 79: r eceive stm-0/stm-1 t ransport - r eceive sf set m onitor i nterval 1 (rsfsmi1 = 0 x 0232) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH221 142 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu sf set threshold register, then the receive stm-0/s tm-1 toh processor block will declare the sf defect condition. n ote : the value that the user writes into these three (3) sf set monitor window registers, specifies the dur ation of the sf defect declaration monitoring period, in ter ms of ms.
XRT86SH221 preliminary 143 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - sf_set_monitor_interval - lsb these read/write bits, along the contents of the re ceive stm-0/stm-1 transport - sf set monitor interv al - byte 2 and byte 1 registers are used to specify the length of the monitoring period (in terms of ms) for sf ( signal failure) defect declaration. when the receive stm-0/stm-1 toh processor block is checking the incoming stm-0/stm-1 signal in order to deter- mine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the us er-specified sf defect declaration monitoring period. if, during this sf defect declaration monitoring period, the receive s tm-0/stm-1 toh processor block accumulates more b2 byte errors tha n that specified within the receive stm-0/stm-1 tra nsport sf set threshold register, then the receive stm-0/stm-1 to h processor block will declare the sf defect condit ion. n otes : 1. the value that the user writes into these three ( 3) sf set monitor window registers, specifies the duration of the sf defect declaration monitoring pe riod, in terms of ms. 2. this particular register byte contains the lsb (l east significant byte) value of the three registers that specify the sf defect declaration monitoring period . bit [7:0] - sf_set_threshold - msb these read/write bits, along the contents of the re ceive stm-0/stm-1 transport - sf set threshold - by te 0 registers are used to specify the number of b2 byte errors that will cause the receive stm-0/stm-1 toh processor block to declare the sf (signal failure) defect con dition. when the receive stm-0/stm-1 toh processor block is checking for declaring the sf defect condition, it will accumulate b2 byte errors throughout the sf defect declaration monitoring period. if the number of ac cumulated b2 byte errors exceeds that value, which is programmed into this and the receive stm-0 transport sf set t hreshold - byte 0 register, then the receive stm-0/stm-1 toh p rocessor block will declare the sf defect condition . n ote : this particular register byte contains the msb (mos t significant byte) value of this 16-bit expression . t able 80: r eceive stm-0/stm-1 t ransport - r eceive sf set m onitor i nterval 0 (rsfsmi0 = 0 x 0233) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 81: r eceive stm-0/stm-1 t ransport - r eceive sf set t hreshold 1 (rsfst1= 0 x 0236) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH221 144 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - sf_set_threshold - lsb these read/write bits, along the contents of the re ceive stm-0/stm-1 transport - sf set threshold - by te 1 registers are used to specify the number of b2 byte errors that will cause the receive stm-0/stm-1 toh processor block to declare the sf (signal failure) defect con dition. when the receive stm-0/stm-1 toh processor block is checking for declaring the sf defect condition, it will accumulate b2 byte errors throughout the sf defect monitoring period. if the number of accumulated b2 byte errors exceeds that which has been programmed into this an d the receive stm-0 transport sf set threshold - by te 1 register, then the receive stm-0/stm-1 toh processo r block will declare the sf defect condition. bit [7:0] - sf_clear_threshold - msb these read/write bits, along the contents of the re ceive stm-0 transport - sf clear threshold - byte 0 registers are used to specify the upper limit for the number of b2 bit errors that will cause the receive stm-0 toh processor block to clear the sf (signal failure) defect condi tion. when the receive stm-0 toh processor block is check ing for clearing the sf defect condition, it will a ccumulate b2 byte errors throughout the sf defect clearance moni toring period. if the number of accumulated b2 byt e errors is less than that programmed into this and the receive stm- 0 transport sf clear threshold - byte 0 register, t hen the receive stm-0 toh processor block clear the sf defe ct condition. bit [7:0] - sf_clear_threshold - lsb these read/write bits, along the contents of the re ceive stm-0 transport - sf clear threshold - byte 1 registers are used to specify the upper limit for the number of b2 bit errors that will cause the receive stm-0 toh processor block to clear the sf (signal failure) defect condi tion. when the receive stm-0 toh processor block is check ing for clearing the sf defect condition, it will a ccumulate b2 byte errors throughout the sf defect clearance moni toring period. if the number of accumulated b2 byt e errors is less than that programmed into this and the receive stm- 0 transport sf clear threshold - byte 1 register, t hen the receive stm-0 toh processor block will clear the sf defect condition. t able 82: r eceive stm-0/stm-1 t ransport - r eceive sf set t hreshold 0 (rsfst0 = 0 x 0237) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 83: r eceive stm-0 t ransport - r eceive sf clear t hreshold 2 (rsfct2= 0 x 023a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 84: r eceive stm-0 t ransport - r eceive sf clear t hreshold 1 (rsfct1 = 0 x 023b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH221 preliminary 145 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - sd_set_monitor_interval - msb these read/write bits, along the contents of the re ceive stm-0 transport - sd set monitor interval - b yte 1 and byte 0 registers are used to specify the length of the m onitoring period (in terms of ms) for sd (signal de grade) defect declara- tion. when the receive stm-0 toh processor block is check ing the incoming stm-0 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user-specified sd de fect declaration mon- itoring period. if, during this sd defect declarat ion monitoring period, the receive stm-0 toh proces sor block accumu- lates more b2 byte errors than that specified withi n the receive stm-0 transport sd set threshold regi ster, then the receive stm-0 toh processor block will declare the sd defect condition. n otes : 1. the value that the user writes into these three ( 3) sd set monitor window registers, specifies the duration of the sd defect declaration monitoring pe riod, in terms of ms. 2. this particular register byte contains the msb (m ost significant byte) value of the three registers that specify the sd defect declaration monitoring period . bit [7:0] - sd_set_monitor_interval - bits 15 throu gh 8 these read/write bits, along the contents of the re ceive stm-0 transport - sd set monitor interval - b yte 2 and byte 0 registers are used to specify the length of the monitoring period (in terms of ms) for sd (sign al degrade) defect declaration. when the receive stm-0 toh processor block is check ing the incoming stm-0 signal in order to determine it it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user-specified sd de fect declaration monitoring period. if, during this sd defect decla ration monitoring period the receive stm-0 toh proc essor block accumulates more b2 byte errors than that specified within the receive stm-0 transport sd set threshol d register, then the receive stm-0 toh processor block will dec lare the sd defect condition. n ote : the value that the user writes into these three (3) sd set monitor window registers, specifies the dur ation of the sd defect declaration monitoring period, in ter ms of ms. t able 85: r eceive stm-0 t ransport - r eceive sd s et m onitor i nterval 0 (rsfct0 = 0 x 023d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 86: r eceive stm-0 t ransport - r eceive sd s et m onitor i nterval 1 (rsdsmi1 = 0 x 023e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 146 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - sd_set_monitor_interval - lsb these read/write bits, along the contents of the re ceive stm-0 transport - sd set monitor interval - b yte 2 and byte 1 registers are used to specify the length of the monitoring period (in terms of ms) for sd (sign al degrade) defect declaration. when the receive stm-0 toh processor block is check ing the incoming stm-0 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user-speciifed sd de fect declaration monitoring period. if, during this sd defect decla ration monitoring period, the receive stm-0 toh pro cessor block accmulattes more b2 byte errors than that specified within the receive stm-0 transport sd set threshol d register, then the receive stm-0 toh processor block will dec lare the sd defect condition. n otes : 1. the value that the user writes into these three ( 3) sd set monitor window registers, specifies the duration of the sd defect declaration monitoring pe riod, in terms of ms. 2. this particular register byte contains the lsb (l east significant byte) value of the three registers that specify the sd defect declaration monitoring period . bit [7:0] - sd_set_threshold - msb these read/write bits, along the contents of the re ceive stm-0 transport - sd set threshold - byte 0 r egisters are used to specify the number of b2 bit errors tha t will cause the receive stm-0 toh processor block to declare the sd (signal degrade) defect condition. when the receive stm-0 toh processor block is check ing for declaring the sd defect condition, it will accumulate b2 byte errors throughout the sd defect declaration mo nitoring period. if the number of accumulated b2 b yte errors exceeds that value, which is programmed into this a nd the receive stm-0 transport sd set threshold - b yte 0 register, then the receive stm-0 toh processor bloc k will declare the sd defect condition. t able 87: r eceive stm-0 t ransport - r eceive sd s et m onitor i nterval 0 (rsdsmi0 = 0 x 023f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 88: r eceive stm-0 t ransport - r eceive sd set t hreshold 1 (rsdst1= 0 x 0242) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH221 preliminary 147 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - sd_set_threshold - lsb these read/write bits, along the contents of the re ceive stm-0 transport - sd set threshold - byte 1 r egisters are used to specify the number of b2 bit errors tha t will cause the receive stm-0 toh processor block to declare an sd (signal degrade) defect condition. when the receive stm-0 toh processor block is check ing for declaring the sd defect condition, it will accumulate b2 byte errors throughout the sd defect monitoring per iod. if the number of accumulated b2 byte errors ex ceeds that which has been programmed into this and the receive stm-0 transport sd set threshold - byte 1 register, then the receive stm-0 toh processor block will declare the sd defec t condition. bit [7:0] - sd_clear_threshold - msb these read/write bits, along the contents of the re ceive stm-0 transport - sd clear threshold - byte 0 registers are used to specify the upper limit for the number of b2 byte errors that will cause the receive stm-0 toh processor block to clear the sd (signal degrade) defect condi tion. when the receive stm-0 toh processor block is check ing for clearing the sd defect condition, it will a ccumulate b2 byte errors throughout the sd defect clearance moni toring period. if the number of accumulated b2 byt e errors is less than that programmed into this and the receive stm- 0 transport sd clear threshold - byte 0 register, t hen the receive stm-0 toh processor block will clear the sd defect condition. bit [7:0] - sd_clear_threshold - lsb these read/write bits, along the contents of the re ceive stm-0 transport - sd clear threshold - byte 1 registers are used to specify the upper limit for the number of b2 byte errors that will cause the receive stm-0 toh processor block to clear the sd (signal degrade) defect condi tion. when the receive stm-0 toh processor block is check ing for clearing the sd defect condition, it will a ccumulate b2 byte errors throughout the sd defect clearance moni toring period. if the number of accumulated b2 byt e errors is less than that programmed into this and the receive stm- 0 transport sd clear threshold - byte 1 register, t hen the receive stm-0 toh processor block will clear the sd defect condition. t able 89: r eceive stm-0 t ransport - r eceive sd set t hreshold 0 (rsdst0 = 0 x 0243) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 90: r eceive stm-0 t ransport - r eceive sd clear t hreshold 1 (rsdct1= 0 x 0246) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 91: r eceive stm-0 t ransport - r eceive sd clear t hreshold 0 (rsdct0 = 0 x 0247) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH221 148 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:1] - unused bit 0 - sef defect condition force this read/write bit-field is used to force the rece ive stm-0 toh processor block (within the correspon ding channel) to declare the sef defect condition. the receive stm-0 toh processor block will then attempt to reacquire framing. writing a 1 into this bit-field configures the rece ive stm-0 toh processor block to declare the sef de fect. the receive stm-0 toh processor block will automaticall y set this bit-field to 0 once it has reacquired fr aming (e.g., has detected two consecutive stm-0 frames with the corr ect a1 and a2 bytes). t able 92: r eceive stm-0 t ransport - f orce sef d efect c ondition r egister (fsdcr = 0 x 024b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused sef force r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 149 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:5] - unused bit 4 - receive section trace message buffer read s election this read/write bit-field is used to specify which of the following receive section trace message buff er segments to read. ? the actual receive section trace message buffer whi ch contains the contents of the most recently recei ved (and accepted) section trace message via the incomi ng stm-0 data-stream. ? the expected receive section trace message buffer which contains the contents of the section trace message that the user expects to receive. the cont ents of this particular buffer are usually specifie d by the user. 0 - executing a read to the receive section trace m essage buffer address space, will return contents w ithin the actual receive section trace message buffer. 1 - executing a read to the receive section trace m essage buffer address space will return contents wi thin the expected receive section trace message buffer. n ote : in the case of the receive stm-1 toh processor bloc k, the receive section trace message buffer is loca ted at address location 0x0400 through 0x043f. bit 3 - receive section trace message accept thresh old this read/write bit-field is used to select the num ber of consecutive times that the receive stm-0 toh processor block must receive a given section trace message, b efore it is accepted, as described below. once a g iven section trace message has been accepted then it can be read out of the actual receive section trace message bu ffer. 0 - the receive stm-0 toh processor block accepts t he section trace message after it has received it t he third time in succession. 1 - the receive stm-0 toh processor block accepts t he section trace message after it has received in t he fifth time in succession. bit 2 - section trace message alignment type this read/write bit-field is used to specify how th e receive stm-0 toh processor block will locate the boundary of the section trace message within the incoming stm-0 data-stream, as indicated below. 0 - message boundary is indicated by line feed. 1 - message boundary is indicated by the presence o f a 1 in the msb of the first byte (within the sect ion trace message). bit [1:0] - receive section trace message length[1 :0] these read/write bit-fields are used to specify the length of the section trace message that the recei ve stm-0 toh processor block will receive. the relationship between the content of these bit-fields and the co rresponding receive section trace message length is presented b elow t able 93: r eceive stm-0 t ransport - r eceive s ection t race m essage b uffer c ontrol r egister (rstmbcr = 0 x 024f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused receive sec- tion trace message buffer read select receive sec- tion trace message accept threshold section trace message alignment type receive section trace mes- sage length[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 150 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - sd_burst_tolerance - msb these read/write bits, along with the contents of t he receive stm-0 transport - sd burst tolerance - b yte 0 registers are used to specify the maximum number of b2 bit errors that the corresponding receive stm-0 toh processor block can accumulate during a single sub- interval period (e.g., an stm-0 frame period), when determining whether or not to declare the sd (signal degrade) d efect condition. n ote : the purpose of this feature is to are used to provi de some level of b2 error burst filtering, when the receive stm-0 toh processor block is accumulating b2 byte e rrors in order to declare the sd defect condition. the user can implement this feature in order to configu re the receive stm-0 toh processor block to detect b2 bit errors in multiple sub-interval periods before it w ill declare the sd defect condition. bit [7:0] - sd_burst_tolerance - lsb these read/write bits, along with the contents of t he receive stm-0 transport - sd burst tolerance - b yte 1 registers are used to specify the maximum number of b2 bit errors that the corresponding receive stm-0 toh processor block can accumulate during a single sub- interval period (e.g., an stm-0 frame period), when determining whether or not to declare the sd (signal degrade) d efect condition. n ote : the purpose of this feature is to are used to provi de some level of b2 error burst filtering, when the receive stm-0 toh processor block is accumulating b2 byte e rrors in order to declare the sd defect condition. the user can implement this feature in order to configu re the receive stm-0 toh processor block to detect b2 bit errors in multiple sub-interval periods before it w ill declare the sd defect condition. trace message length r eceive s ection t race m essage l ength [1:0] r esulting r eceive s ection t race m essage l ength ( in terms of bytes ) 00 1 byte 01 16 bytes 10/11 64 bytes t able 94: r eceive stm-0 t ransport - r eceive sd b urst e rror t olerance 1 (rsdbet1 = 0 x 0252) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 95: r eceive stm-0 t ransport - r eceive sd b urst e rror t olerance 0 (rsdbet0 = 0 x 0253) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH221 preliminary 151 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - sf_burst_tolerance - msb these read/write bits, along with the contents of t he receive stm-0 transport - sf burst tolerance - b yte 0 registers are used to specify the maximum number of b2 bit errors that the corresponding receive stm-0 toh processor block can accumulate during a single sub- interval period (e.g., an stm-0 frame period), when determining whether or not to declare the sf (signal failure) d efect condition. n ote : the purpose of this feature is to are used to provi de some level of b2 error burst filtering, when the receive stm-0 toh processor block is accumulating b2 byte e rrors in order to declare the sf defect condition. the user can implement this feature in order to configu re the receive stm-0 toh processor block to detect b2 bit errors in multiple sub-interval periods before it w ill declare the sf defect condition. bit [7:0] - sf_burst_tolerance - lsb these read/write bits, along with the contents of t he receive stm-0 transport - sf burst tolerance - b yte 1 registers are used to specify the maximum number of b2 bit errors that the corresponding receive stm-0 toh processor block can accumulate during a single sub- interval period (e.g., an stm-0 frame period), when determining whether or not to declare the sf (signal failure) d efect condition. n ote : the purpose of this feature is to are used to provi de some level of b2 error burst filtering, when the receive stm-0 toh processor block is accumulating b2 byte e rrors in order to declare the sf defect condition. the user can implement this feature in order to configu re the receive stm-0 toh processor block to detect b2 bit errors in multiple sub-interval periods before it w ill declare the sf defect condition. t able 96: r eceive stm-0 t ransport - r eceive sf b urst e rror t olerance 1 (rsfbet1 = 0 x 0256) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 97: r eceive stm-0 t ransport - r eceive sf b urst e rror t olerance 0 (rsfbet0 = 0 x 0257) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH221 152 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - sd_clear_monitor_interval - msb these read/write bits, along the contents of the re ceive stm-0 transport - sd clear monitor interval - byte 1 and byte 0 registers are used to specify the length of the monitoring period (in terms of ms) for sd (sign al degrade) defect clearance. when the receive stm-0 toh processor block is check ing the incoming stm-0 signal in order to determine if it should clear the sd defect condition, it will accumulate b 2 byte errors throughout the user-specified sd defe ct clearance monitoring period. if, during this sd defect clear ance monitoring period, the receive stm-0 toh proce ssor block accumulates less b2 byte errors than that programme d into the receive stm-0 transport sd clear thresho ld register, then the receive stm-0 toh processor block will cle ar the sd defect condition. n otes : 1. the value that the user writes into these three ( 3) sd clear monitor window registers, specifies the duration of the sd defect clearance monitoring peri od, in terms of ms. 2. this particular register byte contains the msb (m ost significant byte) value of the three registers that specifiy the sd defect clearance monitoring period. bit [7:0] - sd_clear_monitor_interval - bits 15 thr ough 8 these read/write bits, along the contents of the re ceive stm-0 transport - sd clear monitor interval - byte 2 and byte 0 registers are used to specify the length of the monitoring period (in terms of ms) for sd (sign al degrade) defect clearance. when the receive stm-0 toh processor block is check ing the incoming stm-0 signal in order to determine if it should clear the sd defect condition, it will accumulate b 2 byte errors throughout the user-specified sd defe ct clearance monitoring period. if, during this sd defecf clear ance monitoring period, the receive stm-0 toh proce ssor block accumulates less b2 byte errors than that programme d into the receive stm-0 transport sd clear thresho ld register, then the receive stm-0 toh processor block will cle ar the sd defect condition. n ote : the value that the user writes into these three (3) sd clear monitor window registers, specifies the d uration of the sd defect clearance monitoring period, in terms of ms. t able 98: r eceive stm-0 t ransport - r eceive sd c lear m onitor i nterval 2 (rsdcmi2= 0 x 0259) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 99: r eceive stm-0 t ransport - r eceive sd c lear m onitor i nterval 1 (rsdcmi1 = 0 x 025a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH221 preliminary 153 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - sd_clear_monitor_interval - lsb these read/write bits, along the contents of the re ceive stm-0 transport - sd clear monitor interval - byte 2 and byte 1 registers are used to specify the length of the monitoring period (in terms of ms) for sd (sign al degrade) defect clearance .when the receive stm-0 toh processor block is chec king the incoming stm-0 signal in order to determin e if it should clear the sd defect condition, it will accumulate b 2 byte errors throughout the user-specified sd defe ct clearance monitoring period. if, during this sd defect clear ance monitoring period, the receive stm-0 toh proce ssor block accumulates less b2 byte errors than that programme d into the receive stm-0 transport sd clear thresho ld register, then the receive stm-0 toh processor block will cle ar the sd defect condition n otes : 1. the value that the user writes into these three ( 3) sd clear monitor window registers, specifies the duration of the sd defect clearance monitoring peri od, in terms of ms. 2. this particular register byte contains the lsb (l east significant byte) value of the three registers that specify the sd defect clearance monitoring period. bit [7:0] - sf_clear_monitor_interval - msb these read/write bits, along the contents of the re ceive stm-0 transport - sf clear monitor interval - byte 1 and byte 0 registers are used to specify the length of the monitoring period (in terms of ms) for sf (sign al failure) defect clearance. when the receive stm-0 toh processor block is check ing the incoming stm-0 signal in order to determine if it should clear the sf defect condition, it will accumulate b 2 byte errors throughout the user-specified sf defe ct clearance monitoring period. if, during this sf defect clear ance monitoring period, the receive stm-0 toh proce ssor block accumulates less b2 byte errors than that programme d into the receive stm-0 transport sf clear thresho ld register, then the receive stm-0 toh processor blolck will cl ear the sf defect condition. n otes : 1. the value that the user writes into these three ( 3) sf clear monitor window registers, specifies the duration of the sf defect clearance monitoring peri od, in terms of ms. 2. this particular register byte contains the msb (m ost significant byte) value of the three registers that specify the sf defect clearance monitoring period. t able 100: r eceive stm-0 t ransport - r eceive sd c lear m onitor i nterval 0 (rsdcmi0 = 0 x 025b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_ monitor_ win- dow[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 101: r eceive stm-0 t ransport - r eceive sf c lear m onitor i nterval 2 (rsfcmi2= 0 x 025d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH221 154 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - sf_clear_monitor_interval - bits 15 thr ough 8 these read/write bits, along the contents of the re ceive stm-0 transport - sf clear monitor interval - byte 2 and byte 0 registers are used to specify the length of the monitoring period (in terms of ms) for sf (sign al failure) defect clearance. when the receive stm-0 toh processor block is check ing the incoming stm-0 signal in order to determine if it should clear the sf defect condition, it will accumulate b 2 byte errors throughout the user-specified sf defe ct clearance monitoring period. if, during this sf defect clear ance monitoring period, the receive stm-0 toh proce ssor block accumulates less b2 byte errors than that programme d into the receive stm-0 transport sf clear thresho ld register, then the receive stm-0 toh processor block will cle ar the sf defect condition. n ote : the value that the user writes into these three (3) sf clear monitor window registers, specifies the d uration of the sf defect clearance monitoring period, in terms of ms. bit [7:0] - sf_clear_monitor_interval - lsb these read/write bits, along the contents of the re ceive stm-0 transport - sf clear monitor interval - byte 2 and byte 1 registers are used to specify the length of the monitoring period (in terms of ms) for sf (sign al failure) defect clearance.when the receive stm-0 toh processor bloc k is checking the incoming stm-0 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user-spec ified sf defect clearance monitoring period. if, during this sf de fect clearance monitoring period, the receive stm-0 toh processor block accumulates less b2 byte errors than that pro grammed into the receive stm-0 transport sf clear t hreshold register, then the receive stm-0 toh processor bloc k will clear the sf defect condition. n otes : 1. the value that the user writes into these three ( 3) sf clear monitor window registers, specifies the duration of the sf defect clearance monitoring peri od, in terms of ms. 2. this particular register byte contains the lsb (l east significant byte) value of the three registers that specify the sf defect clearance monitoring period. t able 102: r eceive stm-0 t ransport - r eceive sf c lear m onitor i nterval 1 (rsfcmi1 = 0 x 025e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 103: r eceive stm-0 t ransport - r eceive sf c lear m onitor i nterval 0 (rsfcmi0 = 0 x 025f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH221 preliminary 155 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - transmit path ais upon declaration of the s ection trace message unstable defect condition this read/write bit-field is used to configure the receive stm-0 toh processor block to automatically transmit the path ais (ais-p) indicator via the downstream traff ic (e.g., towards the receive stm-0 poh processor b lock), anytime it declares the section trace message unstable defe ct condition within the incoming stm-0 data-stream. 0 - does not configure the receive stm-0 toh proces sor block to automatically transmit the ais-p indic ator (via the downstream traffic) whenever (and for the duration that) it declares the section trace message unstabl e defect condition. 1 - configures the receive stm-0 toh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) whenever (and for the duration that) it declares the section trace message unstabl e defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 toh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 6 - transmit path ais (ais-p) upon declaration of the section trace message mismatch defect condit ion this read/write bit-field is used to configure the receive stm-0 toh processor block to automatically transmit the path ais (ais-p) indicator via the downstream traff ic (e.g., towards the receive stm-0 poh processor b locks), anytime (and for the duration that) it declares the section trace message mismatch defect condition wi thin the incoming stm-0 data stream. 0 - does not configure the receive stm-0 toh proces sor block to automatically transmit the ais-p indic ator (via the downstream traffic) whenever it declares the sectio n trace mismatch defect condition. 1 - configures the receive stm-0 toh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) whenever (and for the duration that) it declares the section trace message mismat ch defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 toh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 5 - transmit path ais upon declaration of the s ignal failure (sf) defect condition this read/write bit-field is used to configure the receive stm-0 toh processor block to automatically transmit a path ais (ais-p) indicator via the downstream traff ic (e.g., towards the receive stm-0 poh processor b lock), anytime (and for the duration that) it declares the sf defe ct condition. 0 - does not configure the receive stm-0 toh proces sor block to transmit the ais-p indicator (via the downstream traffic) upon declaration of the sf defect. 1 - configures the receive stm-0 toh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) anytime (and for the duration t hat) it declares the sf defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 toh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 4 - transmit path ais upon declaration of the s ignal degrade (sd) defect this read/write bit-field is used to configure the receive stm-0 toh processor block to automatically transmit a path ais (ais-p) indicator via the downstream traff ic (e.g., towards the receive stm-0 poh processor b lock) anytime (and for the duration that) it declares the sd defe ct condition. t able 104: r eceive stm-0 t ransport - a uto ais c ontrol r egister (aaiscr = 0 x 0263) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit ais-p (down- stream) upon section trace mes- sage unsta- ble transmit ais-p (down- stream) upon sec- tion trace message mismatch transmit ais-p (down- stream) upon sf transmit ais-p (down- stream) upon sd unused transmit ais-p (down- stream) upon lof transmit ais-p (down- stream) upon los transmit ais-p (down- stream) enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 156 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 0 - does not configure the receive stm-0 toh proces sor block to transmit the ais-p indicator (via the downstream traffic) upon declaration of the sd defect. 1 - configures the receive stm-0 toh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) anytime (and for the duration t hat) it declares the sd defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 toh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 3 - unused bit 2 - transmit path ais upon declaration of the l oss of frame (lof) defect this read/write bit-field is used to configure the receive stm-0 toh processor block to automatically transmit a path ais (ais-p) indicator via the downstream traff ic (e.g., towards the receive stm-0 poh processor b lock), anytime (and for the duration that) it declares the lof def ect condition. 0 - does not configure the receive stm-0 toh proces sor block to transmit the ais-p indicator (via the downstream traffic) upon declaration of the lof defect. 1 - configures the receive stm-0 toh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) anytime (and for the duration t hat) it declares the lof defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 toh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 1 - transmit path ais upon declaration of the l oss of signal (los) defect this read/write bit-field is used to configure the receive stm-0 toh processor block to automatically transmit a path ais (ais-p) indicator via the downstream traff ic (e.g., towards the receive stm-0 poh processor b lock), anytime (and for the duration that) it declares the los def ect condition. 0 - does not configure the receive stm-0 toh proces sor block to transmit the ais-p indicator (via the downstream traffic) anytime it declares the los defect conditi on. 1 - configures the receive stm-0 toh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) anytime (and for the duration t hat) it declares the los defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 toh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 0 - automatic transmission of ais-p enable this read/write bit-field serves two purposes. it is used to configure the receive stm-0 toh proce ssor block to automatically transmit the path ais ( ais-p) indicator, via the down-stream traffic (e.g., towards the rece ive stm-0 poh processor block), upon detection of a n sf, sd, section trace mismatch, section trace unstable, lof or los defect conditions. it also is used to configure the receive stm-0 toh processor block to automatically transmit a path ai s (ais-p) indicator via the downstream traffic (e.g., towards the receive stm-0 poh processor block) anytime it declares the ais-l defect condition within the incoming stm-0 da tastream. 0 - configures the receive stm-0 toh processor bloc k to not automatically transmit the ais-p indicator (via the downstream traffic) upon declaration of the ais-l d efect condition or any of the above-mentioned defec t conditions. 1 - configures the receive stm-0 toh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) upon declaration of the ais-l d efect or any of the above-mentioned defect conditio ns. n ote : the user must also set the corresponding bit-fields (within this register) to 1 in order to configure the receive stm-0 toh processor block to automatically transmit the ais-p indicator upon declaration of a given al arm/ defect condition.
XRT86SH221 preliminary 157 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:6] - unused bit 5 - transmit e1 ais (via downstream t1/e1s) upo n declaration of the los (loss of signal) defect co ndition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the durati on that) the receive stm-0 toh processor block declares the los defect condition.3 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signal, anytime the receive stm-0 toh processor block declares the los defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 toh processor blo ck declares the los defect condition. bit 4 - transmit e1 ais (via downstream t1/e1s) upo n declaration of the lof (loss of frame) defect con dition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the durati on that) the receive stm-0 toh processor block declares the lof defect condition. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signals, anytime th e receive stm-0 toh processor block declares the lo f defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 toh processor blo ck declares the lof defect condition. bit 3 - transmit e1 ais (via downstream t1/e1s) upo n declaration of the sd (signal degrade) defect con dition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the durati on that) the receive stm-0 toh processor block declares the sd d efect condition. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signals, anytime th e receive stm-0 toh processor block declares the sd defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 toh processor blo ck declares the sd defect condition. bit 2 - transmit e1 ais (via downstream t1/e1s) upo n declaration of the signal failure (sf) defect con dition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signal, anytime (and for the duratio n that) the receive stm-0 toh processor block declares the sf d efect condition. 0 - does not configures all 28 of the egress direct ion transmit e1 framer blocks to automatically tran smit the e1 ais indicator via the downstream e1 signal, anytime the receive stm-0 toh processor block declares the sf defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 toh processor blo ck declares the sf defect condition. r eceive stm-0 t ransport - a uto ais ( in d ownstream e1 s ) c ontrol r egister (aaisdscr= 0 x 026b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit ais (via down- stream t1/ e1s) upon los transmit ais (via down- stream t1/ e1s) upon lof transmit ais (via down- stream t1/ e1s) upon sd transmit ais (via down- stream t1/ e1s) upon sf unused transmit ais (via down- stream t1/ e1s) enable r/o r/o r/w r/w r/w r/w r/o r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 158 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 1 - unused bit 0 - automatic transmission of e1 ais (via the d ownstream e1s) enable this read/write bit-field serves two purposes.it is used to configure each of the 28 egress direction transmit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signal, upon declar ation of either the sf, sd, los or lof defect conditions via the re ceive stm-0 toh processor block. it also is used to configure each of the 28 egress direction transmit e1 framer blocks to automaticall y transmit the e1 ais indicator, via its outbound e1 signals, upon de claration of the ais-l defect condition, via the re ceive stm-0 toh processor block. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator, whenever the receive stm-0 toh processor block declares either the los, lof, sd, sf or ais- l defect conditions. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator, whenever (and for the duration that) the receive st m-0 toh processor block declares either the los, lo f, sd, sf or ais-l defect conditions. bit [7:0] - receive a1, a2 byte error count registe r - msb register this reset-upon-read register, along with the recei ve stm-0/stm-1 transport - a1, a2 byte error count register - byte 0 presents a 16-bit representation of the total num ber of a1 and a2 byte errors that the receive stm-0 /stm-1 toh processor block has detected (within the incoming s tm-0/stm-1 data-stream) since the last read of this register. n ote : this register contains the msb (most significant by te) of this 16-bit expression. bit [7:0] - receive a1, a2 byte error count registe r - lsb register this reset-upon-read register, along with the recei ve stm-0/stm-1 transport - a1, a2 byte error count register - byte 1 presents a 16-bit representation of the to tal number of a1 and a2 byte errors that the receiv e stm-0/stm-1 toh processor block has detected (within the incomi ng stm-0/stm-1 data-stream) since the last read of this register. n ote : this register contains the lsb (least significant b yte) of this 16-bit expression. t able 105: r eceive stm-0/stm-1 t ransport - a1, a2 b yte e rror c ount r egister 1 (a1a2be1 = 0 x 026e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive a1, a2 byte error count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 106: r eceive stm-0/stm-1 t ransport - a1, a2 b yte e rror c ount r egister 0 (a1a2be0 = 0 x 026f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive a1, a2 byte error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 159 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 6.5 receive path overhead operation control register descriptions bit [7:4] - unused bit 3 - check (pointer adjustment) stuff select this read/write bit-field is used to enable/disable the sdh standard recommendation that a pointer inc rement or decrement operation, detected within 3 sdh frames o f a previous pointer adjustment operation (e.g., ne gative stuff, positive stuff) is ignored. 0 - disables this sdh standard implementation. in this mode, all pointer-adjustment operations that a re detected will be accepted. 1 - enables this sdh standard implementation. in t his mode, all pointer-adjustment operations that ar e detected within 3 sdh frame periods of a previous pointer-ad justment operation will be ignored. bit 2 - path - remote defect indicator type select this read/write bit-field is used to configure the receive stm-0 poh processor block to support either the single- bit or the enhanced rdi-p form of signaling, as des cribed below. 0 - configures the receive stm-0 poh processor bloc k to support single-bit rdi-p. in this mode, the receive stm-0 poh processor block will only monitor bit 5, within the g1 byte (of th e incoming spe data), in order to declare and clear the rdi-p defe ct condition. 1 - configures the receive stm-0 poh processor bloc k to support enhanced rdi-p (erdi-p). in this mode, the receive stm-0 poh processor block will monitor bits 5, 6 and 7, within the g1 byte, in order to declare and clear the rdi-p defect condition. bit 1 - rei-p error type this read/write bit-field is used to specify how th e receive stm-0 poh processor block will count (or tally) rei-p events, for performance monitoring purposes. the us er can configure the receive stm-0 poh processor bl ock to increment rei-p events on either a per-bit or per-f rame basis. if the user configures the receive stm-0 poh proces sor block to increment rei-p events on a per-bit ba sis, then it will increment the receive path rei-p error count regist er by the value of the lower nibble within the g1 b yte of the incoming stm-0 data-stream. if the user configures the receive stm-0 poh proces sor block to increment rei-p events on a per-frame basis, then it will increment the receive path rei-p error coun t register each time it receives an stm-0 frame, in which the lower nibble of the g1 byte (bits 1 through 4) are set to a non-zero value. 0 - configures the receive stm-0 poh processor bloc k to count or tally rei-p events on a per-bit basis . 1 - configures the receive stm-0 poh processor bloc k to count or tally rei-p events on a per-frame bas is. bit 0 - b3 error type this read/write bit-field is used to specify how th e receive stm-0 poh processor block will count (or tally) b3 byte errors, for performance monitoring purposes. the u ser can configure the receive stm-0 poh processor b lock to increment b3 byte errors on either a per-bit or per -frame basis. if the user configures the receive stm-0 poh proces sor block to increment b3 byte errors on a per-bit basis, then it will increment the receive path b3 byte error count register by the number of bits (within the b3 byte value) that is in error. if the user configures the receive stm-0 poh proces sor block to increment b3 byte errors on a per-fram e basis, then it will increment the receive path b3 byte error co unt register each time it receives an stm-0 frame t hat contains an erred b3 byte. t able 107: r eceive stm-0 p ath - r eceive c ontrol r egister 0 (rcr0 = 0 x 0283) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused checkstuff rdi-ptype rei-perror type b3 error type r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 160 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 0 - configures the receive stm-0 poh processor bloc k to count b3 byte errors on a per-bit basis 1 - configures the receive stm-0 poh processor bloc k to count b3 byte errors on a per-frame basis. bit [7:1] - unused bit 0 - path trace message unstable defect declared this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the path trace message unstable defect condition. the receive stm-0 poh processor block will declare the path trace message unstable defect condition, whenever the pat h trace message unstable counter reaches the value 8. the path trace message unstable counter will be increme nted for each time that it receives a path trace me ssage that differs from the previously received message. the path trace unstable counter is cleared to 0 wheneve r the receive stm-0 poh processor block has received a given path trace message 3 (or 5) consecutive times. n ote : receiving a given path trace message 3 (or 5) conse cutive times also sets this bit-field to 0 0 - indicates that the receive stm-0 poh processor block is not currently declaring the path trace mes sage unstable defect. 1 - indicates that the receive stm-0 poh processor blolck is currently declaring the path trace messag e unstable defect condition. bit 7 - trace identification mismatch (tim-p) defec t indicator this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the path trace identification mismatch (tim-p) defect c ondition. the receive stm-0 poh processor block wi ll declare the tim-p defect condition, when none of the received 6 4-byte string (received via the j1 byte, within the incoming stm-0 data-stream) matches the expected 64 byte message.t he receive stm-0 poh processor block will clear the tim-p defect condition, when 80% of the received 64 byte string (received via the j1 byte) matches the expec ted 64 byte message. 0 - indicates that the receive stm-0 poh processor block is not currently declaring the tim-p defect c ondition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the tim-p defect condi tion. bit 6 - c2 byte (path signal label byte) unstable d efect declared this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the path signal label byte unstable defect condition. the receive stm-0 poh processor block will declare the c2 (path signal label byte) unstable defect condition, whene ver the c2 byte unstable counter reaches the value 5. the c2 byte unstable counter will be incremented for each time that it receives an spe with a c2 byte value t hat differs from the previously received c2 byte value. the c2 byte unstable counter is cleared to 0 whenever the rece ive stm-0 poh t able 108: r eceive stm-0 p ath - c ontrol r egister (pcr = 0 x 0286) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused path trace message unstable defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 109: r eceive stm-0 p ath - sdh r eceive poh s tatus (rpohs = 0 x 0287) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tim-p defect declared c2 byte unstablede- fect declared uneq-pde- fectdeclared plm-pde- fectdeclared rdi-pde- fectdeclared rdi-p unstable- condition lop-pde- fectdeclared ais-pdefect- declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 161 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 processor block has received 3 (or 5) consecutive s pes that each contains the same c2 byte value.note: receiving a given c2 byte value in 3 (or 5) consecutive spes al so sets this bit-field to 0. 0 - indicates that the receive stm-0 poh processor block is currently not declaring the c2 (path signa l label byte) unstable defect condition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the c2 (path signal la bel byte) unstable defect condition. bit 5 - path - unequipped (uneq-p) defect declared this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the uneq-p defect condition. the receive stm-0 poh pro cessor block will declare the uneq-p defect conditi on, anytime that it receives at least five (5) consecutive stm- 0 frames, in which the c2 byte was set to the value 0x00 (which indicates that the spe is unequipped). the receive stm-0 poh processor block will clear th e uneq-p defect condition, if it receives at least five (5) consecutive stm-0 frames, in which the c2 byte was set to a value other than 0x00. 0 - indicates that the receive stm-0 poh processor block is currently not declaring the uneq-p defect condition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the uneq-p defect cond ition. n ote : :the receive stm-0 poh processor block will not dec lare the uneq-p defect condition if it configured t o expect to receive stm-0 frames with c2 bytes being set to 0x00 (e.g., if the receive stm-0 path - expe cted path label value register -address location= 0x0297 ) is set to 0x00. bit 4 - path payload mismatch (plm-p) defect declar ed this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the plm-p defect condition.the receive stm-0 poh proces sor block will declare the plm-p defect condition, if it receives at least five (5) consecutive stm-0 frames, in whic h the c2 byte was set to a value other than that wh ich it is expecting to receive. whenever the receive stm-0 poh process or block is determining whether or not it should de clare the plm-p defect, it will check the contents of the fol lowing two registers. ? the receive stm-0 path - received path label value register (address location= 0xn196). ? the receive stm-0 path - expected path label value register (address location= 0xn197). the receive stm-0 path - expected path label value register contains the value of the c2 bytes, that t he receive stm-0 poh processor blocks expects to receive.the r eceive stm-0 path - received path label value regis ter contains the value of the c2 byte, that the receive stm-0 poh processor block has most received valida ted (by receiving this same c2 byte in five consecutive stm -0 frames). the receive stm-0 poh processor block will declare the plm-p defect condition if the contents of these two register do not match. the receive stm-0 poh processor block will clear the plm-p defect condition if when ever the contents of these two registers do match. 0 - indicates that the receive stm-0 poh processor block is currently not declaring the plm-p defect c ondition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the plm-p defect condi tion n ote : the receive stm-0 poh processor block will clear th e plm-p defect, upon declaring the uneq-p defect condition. bit 3 - path remote defect indicator (rdi-p) defect declared this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the rdi-p defect condition. if the receive stm-0 poh processor block is configu red to support the single-bit rdi-p function, then it will declare the rdi-p defect condition if bit 5 (within the g1 byte of the incoming stm-0 frame) is set to 1 for r di-p_thrd number of incoming consecutive stm-0 frames. if the receive stm-0 poh processor block is configu red to support the enhanced rdi-p (erdi-p) function , then it will declare the rdi-p defect condition if bits 5, 6 and 7 (within the g1 byte of the incoming stm-0 frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for rdi-p_thrd number of consecutive stm-0 frames. 0 - indicates that the receive stm-0 poh processor block is not currently declaring the rdi-p defect c ondition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the rdi-p defect condi tion. n ote : the user can specify the value for rdi-p_thrd by wr iting the appropriate data into bits 3 through 0 (r di-p thrd) within the receive stm-0 path - sdh receive r di-p register (address location= 0x0293). bit 2 - rdi-p (path - remote defect indicator) unst able defect declared this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the
preliminary XRT86SH221 162 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rdi-p unstable defect condition. the receive stm-0 poh processor block will declare a rdi-p i unstabl e defect condition whenever the rdi-p unstable counter reach es the value rdi-p thrd. the rdi-p unstable count er is incremented for each time that the receive stm-0 po h processor block receives an rdi-p value that diff ers from that of the previous stm-0 frame. the rdi-p unstable co unter is cleared to 0 whenever the same rdi-p value is received in rdi-p_thrd consecutive stm-0 frames. n ote : receiving a given rdi-p value, in rdi-p_thrd consec utive stm-0 frames also clears this bit-field to 0. 0 - indicates that the receive stm-0 poh processor block is not currently declaring the rdi-p unstable defect condition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the rdi-p unstable def ect condition. n ote : the user can specify the value for rdi-p_thrd by wr iting the appropriate data into bits 3 through 0 (r di-p thrd) within the receive stm-0 path - sdh receive r di-p register (address location= 0x0293). bit 1 - loss of pointer indicator (lop-p) defect de clared this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the lop-p (loss of pointer) defect condition. the receive stm-0 poh processor block will declare the lop-p defect condition, if it cannot detect a v alid pointer (h1 and h2 bytes, within the toh) within 8 to 10 consec utive sdh frames. further, the receive stm-0 poh p rocessor block will declare the lop-p defect condition, if i t detects 8 to 10 consecutive ndf events. the rece ive stm-0 poh processor block will clear the lop-p defect conditi on, whenever it detects valid pointer bytes (e.g., the h1 and h2 bytes, within the toh) and normal ndf value for three cons ecutive incoming stm-0 frames. 0 - indicates that the receive stm-0 poh processor block is not declaring the lop-p defect condition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the lop-p defect condi tion. bit 0 - path ais (ais-p) defect declared this read-only bit-field indicates whether or not t he receive stm-0 poh processor block is currently d eclaring the ais-p defect condition. the receive stm-0 poh proc essor block will declare the ais-p defect condition if it detects all of the following conditions within three consec utive incoming stm-0 frames. ? the h1, h2 and h3 bytes are set to an all ones patt ern. ? the entire spe is set to an all ones pattern. the receive stm-0 poh processor block will clear th e ais-p defect condition when it detects a valid st m-0 pointer (h1 and h2 bytes) and a set or normal ndf for three consecutive stm-0 frames. 0 - indicates that the receive stm-0 poh processor block is not currently declaring the ais-p defect c ondition. 1 - indicates that the receive stm-0 poh processor block is currently declaring the ais-p defect condi tion n ote : the receive stm-0 poh processor block will not decl are the lop-p defect condition if it detects an all ones pattern in the h1, h2 and h3 bytes. it will, inste ad, declare the ais-p defect condition. bit [7:5] - unused bit 4 - detection of ais pointer interrupt status this reset-upon-read bit-field indicates whether or not the detection of ais pointer interrupt has occ urred since the last read of this register.if this interrupt is ena bled, then the receive stm-0 poh processor block wi ll generate this interrupt anytime it detects an ais pointer in the incoming stm-0 data stream. t able 110: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt s tatus 2 (rpis2 = 0 x 0289) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused detection of ais pointer interrupt status detection of pointer change interrupt status unused change in tim-p defect condition interrupt status change in path trace message unstable defect condition interrupt status r/o r/o r/o rur rur r/o rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 163 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 n ote : an ais pointer is defined as a condition in which b oth the h1 and h2 bytes (within the toh) are each s et to an all ones pattern. 0 - indicates that the detection of ais pointer int errupt has not occurred since the last read of this register. 1 - indicates that the detection of ais pointer int errupt has occurred since the last read of this reg ister. bit 3 - detection of pointer change interrupt statu s this reset-upon-read bit-field indicates whether or not the detection of pointer change interrupt has occurred since the last read of this register.if this interrupt is enabled, then the receive stm-0 poh processor bloc k will generate an interrupt anytime it accepts a new pointer value (e .g., h1 and h2 bytes, in the toh bytes). 0 - indicates that the detection of pointer change interrupt has not occurred since the last read of t his register. 1 - indicates that the detection of pointer change interrupt has occurred since the last read of this register. bit 2 - unused bit 1 - change in tim-p (trace identification misma tch) defect condition interrupt this reset-upon-read bit-field indicates whether or not the change in tim-p defect condition interrupt has occurred since the last read of this register.if this interr upt is enabled, then the receive stm-0 poh processo r block will generate an interrupt in response to either of the following events. ? whenever the receive stm-0 poh processor block decl ares the tim-p defect condition. ? whenever the receive stm-0 poh processor block clea rs the tim-p defect condition. 0 - indicates that the change in tim-p defect condi tion interrupt has not occurred since the last read of this register. 1 - indicates that the change in tim-p defect condi tion interrupt has occurred since the last read of this register. bit 0 - change in path trace identification message unstable defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in path trace message unstable defe ct condition interrupt has occurred since the last rea d of this register.if this interrupt is enabled, th en the receive stm-0 poh processor block will generate this interrupt in response to either of the following events. ? whenever the receive stm-0 poh processor block dec lare the path trace message unstable defect condition. ? whenever the receive stm-0 poh processor block clea rs the path trace message unstable defect condition. 0 - indicates that the change in path trace message unstable defect condition interrupt has not occurr ed since the last read of this register. 1 - indicates that the change in path trace message unstable defect condition interrupt has occurred s ince the last read of this register. bit 7 - new path trace message interrupt status this reset-upon-read bit-field indicates whether or not the new path trace message interrupt has occur red since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it has accepted (or validated) a new path trace message. t able 111: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt s tatus 1 (rpis1 = 0 x 028a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new path trace message interrupt status detection of rei-p event interrupt status change in uneq-p defect condition interrupt status change in plm-p defect condition interrupt status new c2 byte interrupt status change in c2 byte unstable defect condition interrupt status change in rdi-p unstable defect condition interrupt status new rdi-p value interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 164 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 0 - indicates that the new path trace message inter rupt has not occurred since the last read of this r egister. 1 - indicates that the new path trace message inter rupt has occurred since the last read of this regis ter. bit 6 - detection of rei-p event interrupt status this reset-upon-read bit-field indicates whether or not the detection of rei-p event interrupt has occ urred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects an rei-p event within the incoming stm-0 data-strea m. 0 - indicates that the detection of rei-p event int errupt has not occurred since the last read of this register. 1 - indicates that the detection of rei-p event int errupt has occurred since the last read of this reg ister. bit 5 - change in uneq-p (path - unequipped) defect conditi on interrupt status this reset-upon-read bit-field indicates whether or not the change in uneq-p defect condition interrup t has occurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive stm-0 poh processor block declares the uneq-p defect condition. ? when the receive stm-0 poh processor block clears t he uneq-p defect condition. 0 - indicates that the change in uneq-p defect cond ition interrupt has not occurred since the last rea d of this register. 1 - indicates that the change in uneq-p defect cond ition interrupt has occurred since the last read of this register. n ote : the user can determine if the receive stm-0 poh pro cessor block is currently declaring the uneq-p defe ct condition by reading out the state of bit 5 (uneq-p defect declared) within the receive stm-0 path - s dh receive poh status - byte 0 register (address locat ion= 0xn187). bit 4 - change in plm-p (path - payload mismatch) defect co ndition interrupt status this reset-upon-read bit indicates whether or not t he change in plm-p defect condition interrupt has o ccurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive stm-0 poh processor block declares the plm-p defect condition. ? when the receive stm-0 poh processor block clears the plm-p defect condition. 0 - indicates that the change in plm-p defect condi tion interrupt has not occurred since the last read of this register. 1 - indicates that the change in plm-p defect condi tion interrupt has occurred since the last read of this register. bit 3 - new c2 byte interrupt status this reset-upon-read bit-field indicates whether or not the new c2 byte interrupt has occurred since t he last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it has accepted a new c2 byte. 0 - indicates that the new c2 byte interrupt has no t occurred since the last read of this register. 1 - indicates that the new c2 byte interrupt has oc curred since the last read of this register. bit 2 - change in c2 byte unstable defect condition interru pt status this reset-upon-read bit-field indicates whether or not the change in c2 byte unstable defect conditio n interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? when the receive stm-0 poh processor block declares the c2 byte unstable defect condition. ? when the receive stm-0 poh processor block clears the c2 byte unstable defect condition. 0 - indicates that the change in c2 byte unstable d efect condition interrupt has not occurred since th e last read of this register.
XRT86SH221 preliminary 165 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 1 - indicates that the change in c2 byte unstable d efect condition interrupt has occurred since the la st read of this register. n ote : the user can determine whether or not the receive s tm-0 poh processor block is currently declaring the c2 byte unstable defect condition by reading out the s tate of bit6 (c2 byte unstable defect declared) wit hin the receive stm-0 path - sdh receive poh status - byte 0 register (address location= 0x0287). bit 1 - change in rdi-p unstable defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in rdi-p unstable defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive stm-0 poh processor block declares an rdi-p unstable defect condition. ? when the receive stm-0 poh processor block clears the rdi-p unstable defect condition. 0 - indicates that the change in rdi-p unstable def ect condition interrupt has not occurred since the last read of this register. 1 - indicates that the change in rdi-p unstable def ect condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of rdi-p u nstable defect condition by reading out the state o f bit 2 (rdi-p unstable defect condition) within the receiv e stm-0 path - sdh receive poh status - byte 0 register (address location= 0x0287). bit 0 - new rdi-p value interrupt status this reset-upon-read bit-field indicates whether or not the new rdi-p value interrupt has occurred sin ce the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate this interrupt anytime it receives and validates a new rdi-p value. 0 - indicates that the new rdi-p value interrupt ha s not occurred since the last read of this register . 1 - indicates that the new rdi-p value interrupt ha s occurred since the last read of this register. n ote : the user can obtain the new rdi-p value by reading out the contents of the rdi-p accept[2:0] bit-field s. these bit-fields are located in bits 6 through 4, w ithin the receive stm-0 path - sdh receive rdi-p re gister (address location= 0x0293). bit 7 - detection of b3 byte error interrupt status this reset-upon-read bit-field indicates whether or not the detection of b3 byte error interrupt has o ccurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects a b3 byte error in the incoming stm-0 data stream. 0 - indicates that the detection of b3 byte error i nterrupt has not occurred since the last read of th is interrupt. 1 - indicates that the detection of b3 byte error i nterrupt has occurred since the last read of this i nterrupt. bit 6 - detection of new pointer interrupt status t able 112: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt s tatus 0 (rpis0 = 0 x 028b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 detection of b3 byte error interrupt status detection of new pointer interrupt status detection of unknown pointer interrupt status detection of pointer dec- rement interrupt status detection of pointer increment interrupt status detection of ndf pointer interrupt status change of lop-p defect condition interrupt status change of ais-p defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 166 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu this reset-upon-read indicates whether the detectio n of new pointer interrupt has occurred since the l ast read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects a new pointer value in the incoming stm-0 frame. n ote : pointer adjustments with ndf will not generate this interrupt. 0 - indicates that the detection of new pointer int errupt has not occurred since the last read of this register. 1 - indicates that the detection of new pointer int errupt has occurred since the last read of this reg ister. bit 5 - detection of unknown pointer interrupt stat us this reset-upon-read bit-field indicates whether or not the detection of unknown pointer interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime that it detects a pointer that does not fit into any of the following categories. ? an increment pointer ? a decrement pointer ? an ndf pointer ? an ais (e.g., all ones) pointer ? new pointer 0 - indicates that the detection of unknown pointer interrupt has not occurred since the last read of this register. 1 - indicates that the detection of unknown pointer interrupt has occurred since the last read of this register. bit 4 - detection of pointer decrement interrupt st atus this reset-upon-read bit-field indicates whether or not the detection of pointer decrement interrupt h as occurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects a pointer decrement event. 0 - indicates that the detection of pointer decreme nt interrupt has not occurred since the last read o f this register. 1 - indicates that the detection of pointer decreme nt interrupt has occurred since the last read of th is register.
XRT86SH221 preliminary 167 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 3 - detection of pointer increment interrupt st atus this reset-upon-read bit-field indicates whether or not the detection of pointer increment interrupt h as occurred since the last read of this register. if this inter rupt is enabled, then the receive stm-0 poh process or block will generate an interrupt anytime it detects a pointer increment event. 0 - indicates that the detection of pointer increme nt interrupt has not occurred since the last read o f this register. 1 - indicates that the detection of pointer increme nt interrupt has occurred since the last read of th is register. bit 2 - detection of ndf pointer interrupt status this reset-upon-read bit-field indicates whether or not the detection of ndf pointer interrupt has occ urred since the last read of this register. if this interrupt is enabled, then the receive stm -0 poh processor block will generate an interrupt a nytime it detects an ndf pointer event. 0 - indicates that the detection of ndf pointer int errupt has not occurred since the last read of this register. 1 - indicates that the detection of ndf pointer int errupt has occurred since the last read of this reg ister. bit 1 - change of lop-p defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in lop-p defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? when the receive stm-0 poh processor block declares the lop-p defect condition. ? when the receive stm-0 poh processor block clears the lop-p defect condition. 0 - indicates that the change in lop-p defect condi tion interrupt has not occurred since the last read of this register. 1 - indicates that the change in lop-p defect condi tion interrupt has occurred since the last read of this register. n ote : the user can determine if the receive stm-0 poh pro cessor block is currently declaring the lop-p defec t condition by reading out the state of bit 1 (lop-p defect declared) within the receive stm-0 path - sd h receive poh status - byte 0 register (address locat ion=0x0287). bit 0 - change of ais-p defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change of ais-p defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive stm-0 poh processor block decl ares the ais-p defect condition. ? whenever the receive stm-0 poh processor block clea rs the ais-p defect condition. 0 - indicates that the change of ais-p defect condi tion interrupt has not occurred since the last read of this register. 1 - indicates that the change of ais-p defect condi tion interrupt has occurred since the last read of this register. n ote : the user can determine if the receive stm-0 poh pro cessor block is currently declaring the ais-p defec t condition by reading out the state of bit 0 (ais-p defect declared) within the receive stm-0 path - sd h receive poh status - byte 0 register (address locat ion= 0x0287).
preliminary XRT86SH221 168 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:5] - unused bit 4 - detection of ais pointer interrupt enable this read/write bit-field is used to either enable or disable the detection of ais pointer interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects an ais pointer, in the incoming stm-0 data stream. n ote : an ais pointer is defined as a condition in which b oth the h1 and h2 bytes (within the toh) are each s et to an all ones pattern. 0 - disables the detection of ais pointer interrupt . 1 - enables the detection of ais pointer interrupt. bit 3 - detection of pointer change interrupt enabl e this read/write bit-field is used to either enable or disable the detection of pointer change interrup t. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it has accepted a new pointer value. 0 - disables the detection of pointer change interr upt. 1 - enables the detection of pointer change interr upt. bit 2 - unused bit 1 - change in tim-p (trace identification misma tch) defect condition interrupt this read/write bit-field is used to either enable or disable the change in tim-p condition interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? if the tim-p defect condition is declared. ? if the tim-p defect condition is cleared. 0 - disables the change in tim-p defect condition i nterrupt. 1 - enables the change in tim-p defect condition in terrupt. bit 0 - change in path trace message unstable defec t condition interrupt status this read/write bit-field is used to either enable or disable the change in path trace message unstabl e defect condition interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive stm-0 poh processor block decl ares the path trace message unstable defect condition. whenever the receive stm-0 poh process or block clears the path trace message unstable defect condition. 0 - disables the change in path trace message unsta ble defect condition interrupt. 1 - enables the change in path trace message unstab le defect condition interrupt. t able 113: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt e nable 2 (rpie2 = 0 x 028d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused detection of ais pointer interrupt enable detection of pointer change interrupt enable unused change in tim-p defect condition interrupt enable change in path trace message unstable defect condition interrupt enable r/o r/o r/o r/w r/w r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 169 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - new path trace message interrupt enable this read/write bit-field is used to either enable or disable the new path trace message interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it has accepted (or validated) and new path trace message. 0 - disables the new path trace message interrupt. 1 - enables the new path trace message interrupt. bit 6 - detection of rei-p event interrupt enable this read/write bit-field is used to either enable or disable the detection of rei-p event interrupt. if this interrupt is enabled, then he receive stm-0 poh processor block will generate an interrupt any time it detects an rei-p condition in the coming stm-0 data-stream. 0 - disables the detection of rei-p event interrupt . 1 - enables the detection of rei-p event interrupt. bit 5 - change in uneq-p (path - unequipped) defect condition interrupt enable this read/write bit-field is used to either enable or disable the change in uneq-p defect condition in terrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following conditions ? when the receive stm-0 poh processor block declares the uneq-p defect condition. ? when the receive stm-0 poh processor block clears t he uneq-p defect condition. 0 - disables the change in uneq-p defect condition interrupt. 1 - enables the change in uneq-p defect condition i nterrupt. bit 4 - change in plm-p (path - payload label misma tch) defect condition interrupt enable this read/write bit is used to either enable or dis able the change in plm-p defect condition interrupt . if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive stm-0 poh processor block decl ares the plm-p defect condition. ? whenever the receive stm-0 poh processor block cle ars the plm-p defect condition. 0 - disables the change in plm-p defect condition i nterrupt. 1 - enables the change in plm-p defect condition in terrupt. bit 3 - new c2 byte interrupt enable this read/write bit-field is used to either enable or disable the new c2 byte interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it has accepted a new c2 byte. 0 - disables the new c2 byte interrupt. 1 - enables the new c2 byte interrupt. t able 114: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt e nable 1 (rpie1 = 0 x 028e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new path trace mes- sage inter- rupt enable detection of rei-p event interrupt enable change in uneq-p defect con- dition inter- rupt enable change in plm-p defect con- dition inter- rupt enable new c2 byte interrupt enable change in c2 byte unstable defect con- dition inter- rupt enable change in rdi-p unstable defect con- dition inter- rupt enable new rdi- pvalue inter- rupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 170 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu n ote : the user can obtain the value of this new c2 byte b y reading the contents of the receive stm-0 path - received path label value register (address locatio n= 0x0296). bit 2 - change in c2 byte unstable defect condition interrupt enable this read/write bit-field is used to either enable or disable the change in c2 byte unstable condition interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? when the receive stm-0 poh processor block declares the c2 byte unstable defect condition. ? when the receive stm-0 poh processor block clears t he c2 byte unstable defect condition. 0 - disables the change in c2 byte unstable defect condition interrupt. 1 - enables the change in c2 byte unstable defect c ondition interrupt. bit 1 - change in rdi-p unstable defect condition i nterrupt enable this read/write bit-field is used to either enable or disable the change in rdi-p unstable defect cond ition interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive stm-0 poh processor block dec lares the rdi-p unstable defect condition. ? whenever the receive stm-0 poh processor block clea rs the rdi-p unstable defect condition. 0 - disables the change in rdi-p unstable defect co ndition interrupt. 1 - enables the change in rdi-p unstable defect con dition interrupt. bit 0 - new rdi-p value interrupt enable this read/write bit-field is used to either enable or disable the new rdi-p value interrupt.if this in terrupt is enabled, then the receive stm-0 poh processor block will gen erate this interrupt anytime it receives and valida tes a new rdi- p value. 0 - disables the new rdi-p value interrupt. 1 - enable the new rdi-p value interrupt.
XRT86SH221 preliminary 171 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - detection of b3 byte error interrupt enable this read/write bit-field is used to either enable or disable the detection of b3 byte error interrupt . if this interrupt is enabled, then the receive stm -0 poh processor block will generate an interrupt a nytime it detects a b3-byte error in the incoming stm-0 data-stream. 0 - disables the detection of b3 byte error interru pt. 1 - enables the detection of b3 byte error interrup t. bit 6 - detection of new pointer interrupt enable this read/write bit-field is used to either enable or disable the detection of new pointer interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects a new pointer value in the incoming stm-0 frame. n ote : :pointer adjustments with ndf will not generate thi s interrupt. 0 - disables the detection of new pointer interrupt . 1 - enables the detection of new pointer interrupt. bit 5 - detection of unknown pointer interrupt enab le this read/write bit-field is used to either enable or disable the detection of unknown pointer interru pt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects a pointer adjustment that does not fit into any of th e following categories. an increment pointer. a decrement pointer an ndf pointer ais pointer new pointer. 0 - disables the detection of unknown pointer inte rrupt. 1 - enables the detection of unknown pointer interr upt. bit 4 - detection of pointer decrement interrupt en able this read/write bit-field is used to enable or disa ble the detection of pointer decrement interrupt. if this interrupt is enabled, then the receive stm- 0 toh processor block will generate an interrupt an ytime it detects a pointer-decrement event. 0 - disables the detection of pointer decrement int errupt. 1 - enables the detection of pointer decrement inte rrupt. bit 3 - detection of pointer increment interrupt en able this read/write bit-field is used to either enable or disable the detection of pointer increment inter rupt. if this interrupt is enabled, then the receive stm -0 poh processor block will generate an interrupt a nytime it detects a pointer increment event. 0 - disables the detection of pointer increment int errupt. 1 - enables the detection of pointer increment inte rrupt. bit 2 - detection of ndf pointer interrupt enable this read/write bit-field is used to either enable or disable the detection of ndf pointer interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt an ytime it detects an ndf pointer event. t able 115: r eceive stm-0 p ath - sdh r eceive p ath i nterrupt e nable 0 (rpie0 = 0 x 028f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 detection of b3 byte errorinter- ruptenable detection of new pointer interrupt enable detection of unknown pointer inter- rupt enable detection of pointer dec- rement inter- rupt enable detection of pointer incrementin- terrupt enable detection of ndf pointer- interrupt enable change of lop-p defectcondi- tion interrupt enable change of ais-p defectcondi- tioninterrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 172 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 0 - disables the detection of ndf pointer interrupt . 1 - enables the detection of ndf pointer interrupt. bit 1 - change of lop-p defect condition interrupt enable this read/write bit-field is used to either enable or disable the change in lop (loss of pointer) cond ition interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? when the receive stm-0 poh processor block declares the lop-p defect condition condition. ? when the receive stm-0 poh processor block clears t he lop-p defect condition. 0 - disable the change of lop-p defect condition in terrupt. 1 - enables the change of lop-p defect condition in terrupt. n ote : the user can determine the current state of the lop -p defect condition by reading out the contents of bit 1 (lop-p defect declared) within the receive stm-0 pa th - sdh receive poh status - byte 0 (address location= 0x0287). bit 0 - change of ais-p defect condition interrupt enable this read/write bit-field is used to either enable or disable the change of ais-p (path ais) defect co ndition interrupt. if this interrupt is enabled, then the receive stm- 0 poh processor block will generate an interrupt in response to either of the following events. ? when the receive stm-0 poh processor block declares the ais-p defect condition. ? when the receive stm-0 poh processor block clears t he ais-p defect condition. 0 - disables the change of ais-p defect condition i nterrupt. 1 - enables the change of ais-p defect condition in terrupt. n ote : the user can determine the current state of the ais -p defect condition by reading out the contents of bit 0 (ais-p defect declared) within the receive stm-0 pa th - sdh receive poh status - byte 0 (address location= 0x0287).
XRT86SH221 preliminary 173 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - unused bit [6:4] - accepted rdi-p value these read-only bit-fields contain the value of the most recently accepted rdi-p (e.g., bits 5, 6 and 7 within the g1 byte) value that has been accepted by the receive s tm-0 poh processor block. n ote : a given rdi-p value will be accepted by the receive stm-0 poh processor block, if this rdi-p value has been consistently received in rdi-p threshold[3:0] numbe r of stm-0 frames. bit [3:0] - rdi-p threshold[3:0] these read/write bit-fields are used to defined the rdi-p acceptance threshold for the receive stm-0 p oh processor block. the rdi-p acceptance threshold is the number of con secutive stm-0 frames, in which the receive stm-0 p oh processor block must receive a given rdi-p value, b efore it accepts or validates it. the most recently accepted rdi-p value is written i nto the rdi-p accept[2:0] bit-fields, within this r egister. bit [7:0] - received filtered c2 byte value these read-only bit-fields contain the value of the most recently accepted c2 byte, via the receive st m-0 poh processor block. the receive stm-0 poh processor block will accept a c2 byte value (and load it into these bit-fields) if it has received a consistent c2 byte, in five (5) consecutive stm-0 frames. n ote : the receive stm-0 poh processor block uses this reg ister, along the receive stm-0 path - expected path label value register (address location = 0x0297), w hen declaring or clearing the uneq-p and plm-p defe ct conditions. t able 116: r eceive stm-0 p ath - sdh r eceive rdi-p r egister (rrdipr = 0 x 0293) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused rdi-p_accept[2:0] rdi-p threshold[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 117: r eceive stm-0 p ath - r eceived p ath l abel v alue (rplv = 0 x 0296) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 received_c2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 1 1 1 1 1 1 1 1
preliminary XRT86SH221 174 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - expected c2 byte value these read/write bit-fields are used to specify the c2 (path label byte) value, that the receive stm-0 poh processor block should expect when declaring or cle aring the uneq-p and plm-p defect conditions. if the contents of the received c2 byte value[7:0] (see receive stm-0 path - received path label value register) matches the contents in these register, then the re ceive stm-0 poh will not declare any defect conditi ons. n ote : the receive stm-0 poh processor block uses this reg ister, along with the receive stm-0 path - receive path label value register (address location = 0x029 6), when declaring or clearing the uneq-p and plm-p defect conditions. bit [7:0] - b3 byte error count - msb this reset-upon-read register, along with receive s tm-0 path - b3 byte error count register - bytes 2 through 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a b3 byte error. n otes : 1. if the receive stm-0 poh processor block is confi gured to count b3 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming stm- 0 spe) that are in error. 2. if the receive stm-0 poh processor block is confi gured to count b3 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 spe that contains an er red b3 byte. t able 118: r eceive stm-0 p ath - e xpected p ath l abel v alue (eplv = 0 x 0297) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 expected_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 119: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 3 (b3becr3 = 0 x 0298) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 175 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - b3 byte error count (bits 23 through 16 ) this reset-upon-read register, along with receive s tm-0 path - b3 byte error count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a b3 byte error. n otes : 1. if the receive stm-0 poh processor block is confi gured to count b3 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming stm- 0 spe) that are in error. 2. if the receive stm-0 poh processor block is confi gured to count b3 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 spe that contains an er red b3 byte. bit [7:0] - b3 byte error count - (bits 15 through 8) this reset-upon-read register, along with receive s tm-0 path - b3 byte error count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a b3 byte error. n otes : 1. if the receive stm-0 poh processor block is confi gured to count b3 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits , within the b3 byte (of each incoming stm-0 spe) t hat are in error. 2. if the receive stm-0 poh processor block is confi gured to count b3 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it rec eives an stm-0 spe that contains an erred b3 byte. t able 120: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 2 (b3becr2 = 0 x 0299) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 121: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 1 (b3becr1 = 0 x 029a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 176 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - b3 byte error count - lsb this reset-upon-read register, along with receive s tm-0 path - b3 byte error count register - bytes 3 through 1 function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a b3 byte error. n otes : 1. if the receive stm-0 poh processor block is confi gured to count b3 byte errors on a per-bit basis, t hen it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming stm- 0 spe) that are in error. 2. f the receive stm-0 poh processor block is config ured to count b3 byte errors on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 spe that contains an er red b3 byte. bit [7:0] - rei-p event count - msb this reset-upon-read register, along with receive s tm-0 path - rei-p error count register - bytes 2 th rough 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a path - remote error indicator event within the incoming st m-0 spe data-stream. n otes : 1. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-value w ithin the rei-p field of the incoming g1 byte withi n each incoming stm-0 spe. 2. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-frame basis, t hen it will increment this 32 bit counter each time that it rec eives an stm-0 spe that contains a non-zero rei-p v alue. t able 122: r eceive stm-0 p ath - b3 b yte e rror c ount r egister 0 (b3becr0 = 0 x 029b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 123: r eceive stm-0 p ath - rei-p e vent c ount r egister 3 (reipecr3 = 0 x 029c) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 177 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - rei-p event count (bits 23 through 16) this reset-upon-read register, along with receive s tm-0 path - rei-p error count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a path - remote error indicator event within the inconing st m-0 spe data-stream. n otes : 1. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-va lue within the rei-p field of the incoming g1 byte within each incoming stm-0 frame. 2. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 spe that contains a non -zero rei-p value. bit [7:0] - rei-p event count - (bits 15 through 8) this reset-upon-read register, along with receive s tm-0 path - rei-p error count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a path - remote error indicator event within the incoming st m-0 spe data-stream. n otes : 1. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-va lue within the rei-p field of the incoming g1 byte within each incoming stm-0 spe. 2. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 spe that contains a non -zero rei-p value t able 124: r eceive stm-0 p ath - rei-p e vent c ount r egister 2 (reipecr2 = 0 x 029d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 125: r eceive stm-0 p ath - rei-p e vent c ount r egister 1 (reipecr1 = 0 x 029e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 178 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - rei-p event count - lsb this reset-upon-read register, along with receive s tm-0 path - rei-p error count register - bytes 3 th rough 1, function as a 32 bit counter, which is incremented anytime the receive stm-0 poh processor block detec ts a path - remote error indicator event within the incoming st m-0 spe data-stream. n otes : 1. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-bit basis, the n it will increment this 32 bit counter by the nibble-va lue within the rei-p field of the incoming g1 byte. 2. if the receive stm-0 poh processor block is confi gured to count rei-p events on a per-frame basis, then it will increment this 32 bit counter each tim e that it receives an stm-0 spe that contains a non -zero rei-p value. bit [7:6] - unused bit 5 - new message ready this read/write bit-field indicates whether or not the receive path trace message buffer has received a new expected value. 0 - indicates no new expected value has been downlo aded into the receive j1 trace buffer. 1 - indicates a new expected value has been downloa ded into the receive j1 trace buffer and can be use d to make comparisons with the accepted j1 message. bit 4 - receive section trace message buffer read s election this read/write bit-field is used to specify which of the following receive path trace message buffer segments to read. a. the actual receive path trace message buffer. the actual receive path trace message buffer contai ns the contents of the most recently received (and accepte d) path trace message via the incoming stm-0 data-s tream. b. the expected receive path trace message buffer. the expected receive path trace message buffer co ntains the contents of the path trace message that the use r expects to receive. the contents of this particu lar buffer are usually specified by the user. 0 - executing a read to the receive j1 trace buffer , will return contents within the valid message buf fer. 1 - executing a read to the receive j1 trace buffer , will return contents within the expected message buffer. n ote : in the case of the receive stm-0 poh processor bloc k, the receive j1 trace buffer is located at addres s location 0x0500 through 0x053f. t able 126: r eceive stm-0 p ath - rei-p e vent c ount r egister 0 (reipecr0 = 0 x 029f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 127: r eceive stm-0 p ath - r eceive p ath t race m essage b uffer c ontrol r egister (rptmbcr = 0 x 02a3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused new message ready receive path trace message buffer read select receive path trace message accept threshold path trace message alignment type receive path trace message length[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 179 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 3 - path trace message accept threshold this read/write bit-field is used to select the num ber of consecutive times that the receive stm-0 poh processor block must receive a given receive trace message, b efore it is accepted and loaded into the receive pa th trace message. 0 - the receive stm-0 poh processor block accepts t he path trace message after it has received it the third time in succession. 1 - the receive sdh poh processor block accepts the incoming path trace message after it has received in the fifth time in succession. bit 2 - path trace message alignment type this read/write bit-field is used to specify have t he receive stm-0 poh processor block will locate th e boundary of the j1 trace message. 0 - message boundary is indicated by line feed. 1 - message boundary is indicated by the presence o f a 1 in the msb of a the first byte (within the j1 trace message). bit [1:0] - path trace message length[1:0] these read/write bit-fields are used to specify the length of the receive path trace message that the receive stm- 0 poh processor block will receive. the relationsh ip between the content of these bit-fields and the corresponding receive path trace message length is presented belo w. bit [7:2] - unused bit [1:0] - current pointer value - msb these read-only bit-fields, along with that from th e receive stm-0 path - pointer value - byte 0 regis ter combine to reflect the current value of the pointer that th e receive stm-0 poh processor block is using to loc ate the spe within the incoming stm-0 data stream.note these register bits comprise the upper byte value o f the pointer value. receive trace path message length msg length[1:0] r esulting p ath t race m essage l ength 00 1 byte 01 16 bytes 10/11 64 bytes t able 128: r eceive stm-0 p ath - p ointer v alue 1 (pv1 = 0 x 02a6) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused current_pointer val- uemsb[9:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 180 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - current pointer value - lsb these read-only bit-fields, along with that from th e receive stm-0 path - pointer value - byte 1 regis ter combine to reflect the current value of the pointer that th e receive stm-0 poh processor block is using to loc ate the spe within the incoming stm-0 data stream.note these register bits comprise the lower byte value o f the pointer value. bit [7:0] - defect_c2_byte_value[7:0] these read/write bit-fields are used to configure t he receive stm-0 poh processor block to automatical ly force the transmission of the e1 ais pattern (in the egre ss direction of all 28 channels) anytime it accepts a c2 byte value matching that written into this register. n ote : the chip will only automatically transmit the e1 ai s pattern if bit 1 (defect c2 byte downstream ais e nable), within the receive stm-0 path - receive auto ais - c2 byte control register is set to 1. bit [7:2] - unused bit 1] - defect c2 byte downstream ais enable this bit enables downstream ais insertion when the received c2 matches the c2 defect value specified i n the defect_c2_value. 0 - disable 1 - enable bit 0 - unused t able 129: r eceive stm-0 p ath - p ointer v alue 0 (pv0 = 0 x 02a7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 current_pointer_value_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 130: r eceive stm-0 p ath - r eceive a uto ais - c2 b yte v alue r egister (aisc2vr = 0 x 02b9) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 defect_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 131: r eceive stm-0 p ath - r eceive a uto ais - c2 b yte c ontrol r egister (aisc2cr = 0 x 02ba) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused defect c2 byte down- stream ais enable unused r/o r/o r/o r/o r/o r/o r/w r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 181 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - unused bit 6 - transmit path ais (downstream) upon declara tion of the unstable c2 byte defect condition this read/write bit-field is used to configure the receive stm-0 poh processor block to automatically transmit the path ais (ais-p) indicator via the downstream traff ic (e.g., towards each of the 28 egress direction t ransmit e1 framer blocks), anytime (and for the duration that) it dec lares the unstable c2 byte defect condition within the incoming stm- 0 data-stream. 0 - does not configure the receive stm-0 poh proces sor block to automatically transmit the ais-p indic ator (via the downstream traffic) whenever it declares the unstab le c2 byte defect condition. 1 - configures the receive stm-0 poh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) whenever it declares the unsta ble c2 byte defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 poh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 5 - transmit path ais (downstream) upon declara tion of the uneq-p (path - unequipped) defect condi tion this read/write bit-field is used to configure the receive stm-0 poh processor block to automatically transmit the path ais (ais-p) indicator via the downstream traff ic (e.g., towards each of the 28 egress direction t ransmit e1 framer blocks), anytime (and for the duration that) it dec lares the uneq-p defect condition. 0 - does not configure the receive stm-0 poh proces sor block to automatically transmit the ais-p indic ator (via the downstream traffic) whenever it declares the uneq-p defect condition. 1 - configures the receive stm-0 poh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) whenever it declares the uneq-p defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 poh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 4 - transmit path ais (downstream) upon declara tion of the plm-p (path - payload label mismatch) d efect condition this read/write bit-field is used to configure the receive stm-0 poh processor block to automatically transmit the path ais (ais-p) indicator via the downstream traff ic (e.g., towards each of the 28 egress direction t ransmit e1 framer blocks), anytime (and for the duration that) it dec lares the plm-p defect condition. 0 - does not configure the receive stm-0 poh proces sor block to automatically transmit the ais-p indic ator (via the downstream traffic) whenever it declares the plm-p defect condition. 1 - configures the receive stm-0 poh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) whenever it declares the plm-p defect condition.note n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 poh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 3 - transmit path ais (downstream) upon declara tion of the path trace message unstable defect cond ition this read/write bit-field is used to configure the receive stm-0 poh processor block to automatically transmit the path ais (ais-p) indicator via the downstream traff ic (e.g., towards each of the 28 egress direction t ransmit e1 framer blocks), anytime (and for the duration that) it dec lares the path trace message unstable defect condit ion within the t able 132: r eceive stm-0 p ath - auto ais c ontrol r egister (autoacr = 0 x 02bb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit ais-p (down- stream) upon c2 byte unstable transmit ais-p (down- stream) upon uneq-p transmit ais-p (down- stream) upon plm-p transmit ais-p (down- stream) upon path trace message unstable transmit ais-p (down- stream) upon tim-p transmit ais-p (down- stream) upon lop-p transmit ais-p (down- stream) enable r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 182 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu incoming stm-0 data-stream. 0 - does not configure the receive stm-0 poh proces sor block to automatically transmit the ais-p indic ator (via the downstream traffic) whenever it declares the path t race message unstable defect condition. 1 - configures the receive stm-0 poh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic) whenever it declares the path t race message unstable defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 poh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 2 - transmit path ais (downstream) upon declara tion of the tim-p (path trace message identificatio n mismatch) defect condition this read/write bit-field is used to configure the receive stm-0 poh processor block to automatically transmit a path ais (ais-p) indicator via the downstream traff ic (e.g., towards each of the 28 egress direction t ransmit e1 framer blocks), anytime (and for the duration that) it dec lares the tim-p defect condition within the incomin g stm-0 data- stream. 0 - does not configure the receive stm-0 poh proces sor block to transmit the ais-p indicator (via the downstream traffic) whenever it declares the tim-p defect cond ition. 1 - configures the receive stm-0 poh processor bloc k to transmit the ais-p indicator (via the downstre am traffic) whenever it declares the tim-p defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 poh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 1 - transmit path ais (downstream) upon detecti on of loss of pointer (lop-p) defect condition this read/write bit-field is used to configure the receive stm-0 poh processor block to automatically transmit the path ais (ais-p) indicator via the downstream traff ic (e.g., towards each of the 28 egress direction t ransmit e1 framer blocks), anytime (and for the duration that) it dec lares the lop-p defect condition within the incomin g stm-0 data- stream. 0 - does not configure the receive stm-0 poh proces sor block to automatically transmit the ais-p indic ator (via the downstream traffic, towards the corresponding trans mit sdh poh processor block) whenever it declares t he lop-p defect condition. 1 - configures the receive stm-0 poh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic, towards the corresponding trans mit sdh poh processor block) whenever it declares t he lop-p defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive stm-0 poh processor block to automatically transmit the ais-p indicator , in response to this defect condition. bit 0 - automatic transmission of ais-p enable this read/write bit-field serves two purposes. ? it is used to configure the receive stm-0 poh proce ssor block to automatically transmit the path ais indicator, via the down-stream traffic (e.g., towar ds each of the 28 egress direction transmit e1 fram er blocks), upon detection of an uneq-p, plm-p, lop-p or los conditions. ? it also is used to configure the receive stm-0 poh processor block to automatically transmit a path (a is-p) indicator via the downstream traffic (e.g., towards each of the 28 egress direction transmit e1 framer blocks) anytime it detects an ais-p condition in th e incoming stm-0 data-stream. 0 - configures the receive stm-0 poh processor bloc k to not automatically transmit the ais-p indicator (via the downstream traffic, towards each of the 28 egress d irection transmit e1 framer blocks) whenever it dec lares any of the above-mentioned defect conditions. 1 - configures the receive stm-0 poh processor bloc k to automatically transmit the ais-p indicator (vi a the downstream traffic, towards each of the 28 egress d irection transmit e1 framer blocks) whenever it dec lares any of the above-mentioned defect condition. n ote : the user must also set the corresponding bit-fields (within this register) to 1 in order to configure the receive stm-0 poh processor block to automatically transmit the ais-p indicator upon detection of a given alar m/ defect condition.
XRT86SH221 preliminary 183 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - unused bit 6 - transmit e1 ais (via downstream t1/e1s) upon decla ration of the lop-p defect condition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signal, anytime (and for the duratio n that) the receive stm-0 poh processor block declares the lop- p defect condition. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signal, anytime the receive stm-0 poh processor block declares the lop -p defect. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signal, anytime (and for the duration that) the receive stm-0 poh processor bloc k declares the lop-p defect. bit 5 - transmit e1 ais (via downstream t1/e1s) upon declar ation of the plm-p defect condition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signal, anytime (and for the duratio n that) the receive stm-0 poh processor block declares the plm- p defect condition. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signals, anytime th e receive stm-0 poh processor block declares the pl m-p defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 poh processor blo ck declares the plm-p defect condition. bit 4 - unused bit 3 - transmit e1 ais (via downstream t1/e1s) upon declar ation of the uneq-p defect condition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the durati on that) the receive stm-0 poh processor block declares the uneq -p defect condition. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signals, anytime th e receive stm-0 poh processor block declares the un eq-p defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 poh processor blo ck declares the uneq-p defect condition. bit 2 - transmit e1 ais (via downstream t1/e1s) upon declar ation of the tim-p defect condition this read/write bit-field is used to configure each of the 28 egress direction transmit e1 framer bloc ks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the durati on that) the receive stm-0 poh processor block declares the tim- p defect condition. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signals, anytime th e receive stm-0 poh processor block declares the ti m-p defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 poh processor blo ck declares t able 133: r eceive stm-0 p ath - sdh r eceive a uto a larm r egister (raar = 0 x 02c3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit ais (via downstream t1/e1s) upon lop-p transmit ais (via down- stream t1/ e1s) upon- plm-p unused transmit ais (via down- stream t1/ e1s) upon uneq-p transmit ais (via down- stream t1/ e1s) upon tim-p transmit ais (via down- stream t1/ e1s) upon ais-p unused r/w r/w r/w r/o r/w r/w r/w r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 184 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu the tim-p defect condition. bit 1 - transmit e1 ais (via downstream t1/e1s) upon ais-p this read/write bit-field is used to configure eac h of the 28 egress direction transmit e1 framer blo cks to automatically transmit the e1 ais indicator via the downstream e1 signals, anytime (and for the durati on that) the receive stm-0 poh processor block declares the ais- p defect condition. 0 - does not configure all 28 of the egress directi on transmit e1 framer blocks to automatically trans mit the e1 ais indicator via the downstream e1 signal, anytime the receive stm-0 poh processor block declares the ais -p defect condition. 1 - configures all 28 of the egress direction trans mit e1 framer blocks to automatically transmit the ais-p indicator via the downstream e1 signals, anytime (and for the duration that) the receive stm-0 poh processor blo ck declares the ais-p defect condition. bit 0 - unused bit [7:0] - receive negative pointer adjustment count - msb these reset-upon-read bits, along with that in rece ive stm-0 path - receive negative pointer adjustmen t count register - byte 0 present a 16-bit representation o f the number of negative (or decrementing) pointer adjustments that the receive stm-0 poh processor block has detected since the last read of these registers. n ote : this register contains the msb (most significant bi ts) of this 16-bit expression. bit [7:0] - receive negative pointer adjustment cou nt - lsb these reset-upon-read bits, along with that in rece ive stm-0 path - receive negative pointer adjustmen t count register - byte 1 present a 16-bit representation o f the number of negative (or decrementing) pointer adjustments that the receive stm-0 poh processor block has detected since the last read of these registers. n ote : this register contains the lsb (least significant b its) of this 16-bit expression. t able 134: r eceive stm-0 p ath - r eceive n egative p ointer a djustment c ount r egister 1 (rnpacr1 = 0 x 02c4) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive negative pointer adjustment count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 135: r eceive stm-0 p ath - r eceive n egative p ointer a djustment c ount r egister 0 (rnpacr0 = 0 x 02c5) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive negative pointer adjustment count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 185 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - receive positive pointer adjustment cou nt - msb these reset-upon-read bits, along with that in rece ive stm-0 path - receive positive pointer adjustmen t count register - byte 0 present a 16-bit representation o f the number of positive (or incrementing) pointer adjustments that the receive stm-0 poh processor block has detected since the last read of these registers. n ote : this register contains the msb (most significant bi ts) of this 16-bit expression. bit [7:0] - receive positive pointer adjustment cou nt - lsb these reset-upon-read bits, along with that in rece ive stm-0 path - receive positive pointer adjustmen t count register - byte 1 present a 16-bit representation o f the number of positive (or incrementing) pointer adjustments that the receive stm-0 poh processor block has detected since the last read of these registers. n ote : this register contains the lsb (least significant bits) of this 16-bit expression. bit [7:0] - j1 byte captured value[7:0] these read-only bit-fields contain the value of the j1 byte, within the most recently received stm-0 f rame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new j1 byte value. t able 136: r eceive stm-0 p ath - r eceive p ositive p ointer a djustment c ount r egister 1 (rppacr1 = 0 x 02c6) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive positive pointer adjustment count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 137: r eceive stm-0 p ath - r eceive p ositive p ointer a djustment c ount r egister 0 (rppacr0 = 0 x 02c7) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive positive pointer adjustment count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 138: r eceive stm-0 p ath - r eceive j1 b yte c apture r egister (rj1bcr = 0 x 02d3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 j1_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 186 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - b3 byte captured value[7:0] these read-only bit-fields contain the value of the b3 byte, within the most recently received stm-0 f rame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new b3 byte value. bit [7:0] - c2 byte captured value[7:0] these read-only bit-fields contain the value of the c2 byte, within the most recently received stm-0 f rame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new c2 byte value. bit [7:0] - g1 byte captured value[7:0] these read-only bit-fields contain the value of the g1 byte, within the most recently received stm-0 f rame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new g1 byte value. bit [7:0] - f2 byte captured value[7:0] these read-only bit-fields contain the value of the f2 byte, within the most recently received stm-0 f rame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new f2 byte value. t able 139: r eceive stm-0 p ath - r eceive b3 b yte c apture r egister (rb3bcr = 0 x 02d7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 140: r eceive stm-0 p ath - r eceive c2 b yte c apture r egister (rc2bcr = 0 x 02db) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 141: r eceive stm-0 p ath - r eceive g1 b yte c apture r egister (rg1bcr = 0 x 02df) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g1_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 142: r eceive stm-0 p ath - r eceive f2 b yte c apture r egister (rf2bcr = 0 x 02e3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 187 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - h4 byte captured value[7:0] these read-only bit-fields contain the value of the h4 byte, within the most recently received stm-0 f rame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new h4 byte value. bit [7:0] - z3 byte captured value[7:0] these read-only bit-fields contain the value of the z3 byte, within the most recently received stm-0 f rame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new z3 byte value. bit [7:0] - z4 (k3) byte captured value[7:0] these read-only bit-fields contain the value of the z4 (k3) byte, within the most recently received st m-0 frame. this particular value is stored in this register for one stm-0 frame period. during the next stm-0 frame p eriod, this value will be overridden with a new z4 (k3) byte value. bit [7:0] - z5 byte captured value[7:0] these read-only bit-fields contain the value of the z5 byte, within the most recently received stm-0 f rame. this particular value is stored in this register fo r one stm-0 frame period. during the next stm-0 fr ame period, this value will be overridden with a new z5 byte value. t able 143: r eceive stm-0 p ath - r eceive h4 b yte c apture r egister (rh4bcr = 0 x 02e7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h4_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 144: r eceive stm-0 p ath - r eceive z3 b yte c apture r egister (rz3bcr = 0 x 02eb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z3_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 145: r eceive stm-0 p ath - r eceive z4 (k3) b yte c apture r egister (rz4bcr = 0 x 02ef) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z4(k3)_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 146: r eceive stm-0 p ath - r eceive z5 b yte c apture r egister (rz5bcr = 0 x 02f3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z5_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 188 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 6.6 transmit transport overhead port control registe r descriptions bit [7:4] - reserved bit [3:0] - control pointer [3:0] this pointer value is used to select the slot in cu rrent txsoh group (up to 3) to be programmed. 0000 - slot 0 0001 - slot 1 0010 - slot 2 0011 - 1111 - not used bit [7:3] - reserved bit 2 - multiplex section auto ais alarm enable when enabled, the ms-ais will be automatically inse rted upon receiving ms-ais alarm from upstream. 0 - disabled 1 - auto ms-ais enabled bit 1 - regenerator section data communication chan nel relocate soh passthrough must be enabled for this bit to hav e function. the first channel upstream rsdcc (d1,d 2,d3) will be mapped to rsdcc location of the second slot of this channel. for example, the rsdcc of a stm1 au4 in put stream for slot 0 will be inserted into slot 4 which is th e second slot of this stm1. the rsdcc for slot 0 w ill be inserted internally either through external interface or internal regis ter. 0 - disabled 1 - relocate rsdcc (d1,d2,d3) bit 0 - multiplex section data communication channe l relocate soh passthrough must be enabled for this bit to hav e function. the first channel upstream msdcc (d4-d 12) will be mapped to msdcc location of the second slot of this channel. for example, the msdcc of a stm1 au4 in put stream for slot 0 will be inserted into slot 4 which is th e second slot of this stm1. the msdcc for slot 0 w ill be inserted internally either through external interface or internal regis ter. 0 - disabled 1 - relocate msdcc (d4-d12) t able 147: t ransmit stm-0 s ection c ontrol r egister 3 (tscr3 0 x 0700 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved cntl_ptr[3:0] ro ro ro ro r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 148: t ransmit stm-0 s ection c ontrol r egister 2 (tscr2 0 x 0701 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved auto ms-ais_en rsdcc relocate msdcc relocate ro ro ro ro ro r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 189 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - reserved bit 6 - stm-n overhead insert this read/write bit-field permits the user to confi gure the txsoh input port to insert the soh for the outbound stm- 0 or stm-1 signal. 0 - disabled 1 - enabled bit 5 - e2 byte insert method this read/write bit-field is used to specify the so urce of the contents of the e2 byte, within the tra nsmit output stm- 0 or stm-1 data stream. 0 - e2 byte is obtained from txsoh serial input por t. 1 - e2 byte is obtained from the contents within th e transmit section - e2 byte value register (addres s location = 0x0747). this selection provides the user with soft ware control over the value of the outbound e2 byte . bit 4 - e1 byte insert method this read/write bit-field is used to specify the so urce of the contents of the e1 byte, within the tra nsmit output stm- 0 or stm-1 data stream. 0 - e1 byte is obtained from txsoh serial input por t. 1 - e1 byte is obtained from the contents within th e transmit section - e1 byte value register (addres s location= 0x0743). this selection provides the user with soft ware control over the value of the outbound e1 byte . bit 3 - f1 byte insert method this read/write bit-field is used to specify the so urce of the contents of the f1 byte, within the tra nsmit output stm- 0 data stream. 0 - f1 byte is obtained from txsoh serial input por t. 1 - f1 byte is obtained from the contents within th e transmit section - f1 byte value register (addres s location= 0x073f). this selection provides the user with soft ware control over the value of the outbound f1 byte . bit 2 - s1 byte insert method this read/write bit-field is used to specify the so urce of the contents of the s1 byte, within the tra nsmit output stm- 0 data stream. 0 - s1 byte is obtained from txsoh serial input por t. 1 - s1 byte is obtained from the contents within th e transmit section - s1 byte value register (addres s location= 0x073b). this selection provides the user with soft ware control over the value of the outbound s1 byte . bit 1 - k1k2 byte insert method this read/write bit-field is used to specify the so urce of the contents of the k1 and k2 bytes, within the transmit output stm-0 data stream. 0 - k1 and k2 bytes are obtained from txsoh serial input port. 1 - k1 and k2 bytes are obtained from the contents within the transmit section - k2 byte value registe r - byte 1 (address location= 0x072e) and the transmit section - k1 byte value register - byte 0 (address locatio n= 0x072f). this selection provides the user with software cont rol over the value of the outbound k1 and k2 bytes. t able 149: t ransmit stm-0 s ection c ontrol r egister 1 (tscr1 0 x 0702 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved stm-n overhead insert e2 insert method e1 insert method f1 insert method s1 insert method k1k2 insert method m0m1 insert method [1] ro r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 190 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 0 - m0m1 byte insert method [1] this read/write bit-field, along with m0m1 insert m ethod[0] (located in the next register 0x0703h) are used to specify the source of the contents of the m0/m1 byt e, within the transmit output stm-0 data stream. th e relationship between these two bit-fields and the corresponding source of the m0/m1 byte is presented below. t able 150: s ource of m0/m1 b yte m0m1 i nsert m ethod [1:0] s ource of m0/m1 b yte 0 0 from the receive stm-0 soh processor block (b2 by te error count). 0 1 obtained from the contents of the transmit stm-0 section - m0/m1 byte value register (address location = 0x0737). 1 0 m0/m1 byte is obtained from the txsoh serial inpu t port. 1 1 from the receive stm-0 soh processor block (b2 by te error count).
XRT86SH221 preliminary 191 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - m0m1 byte insert method [0] this read/write bit-field, along with m0m1 insert m ethod[1] (located in the transmit section - sdh con trol register - byte 1) are used to specify the source of the con tents of the m0/m1 byte, within the transmit output stm-0 data stream. the relationship between these two bit-fields and t he corresponding source of the m0/m1 byte is presen ted below. source of m0/m1 byte bit 6 - undefined section overhead byte value assig nment this read/write bit-field specifies the value assig ned to the undefined section overhead bytes. 0 - undefined section overhead bytes will be assign ed the value 0x00. 1 - undefined section overhead bytes will be assign ed the value 0xff. bit 5 - force multiplex section - remote defect ind icator this read/write bit-field is used to (by software c ontrol) force the transmit stm-0 soh processor bloc k to generate and transmit the ms-rdi indicator to the remote ter minal equipment by forcing bits-2, 1, and 0 of the k2 byte to the value 3b110. 0 - normal operation. 1 - force ms-rdi. n ote : this bit-field is ignored if the transmit stm-0 soh processor block is currently transmitting the muti plex section ais (ms-ais) indicator or los pattern. bit 4 - force multiplex section - alarm indication signal this read/write bit-field is used to (by software c ontrol) force the transmit stm-0 soh processor bloc k to generate and transmit the ms-ais indicator to the remote ter minal equipment. 0 - normal operation. 1 - force ms-ais. n ote : this bit-field is ignored if the transmit stm-0 soh processor block is transmitting the los pattern. bit 3 - force los pattern this read/write bit-field is used to (by software c ontrol) force the transmit stm-0 soh processor bloc k to transmit the los (loss of signal) pattern to the remote term inal equipment. 0 - normal operation. 1 - configures the transmit stm-0 soh processor blo ck to transmit the los pattern. in this case, the t ransmit stm- 0 soh processor block will force all bytes (within the outbound sdh frame) to an all zeros pattern. t able 151: t ransmit stm-0 s ection c ontrol r egister 0 (tscr0 0 x 0703 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 m0m1 insert method [0] udfn soh value force ms-rdi force ms-ais force los pattern scramble enable b2 byte error insert a1a2 byte error insert r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 m0m1 i nsert m ethod [1:0] s ource of m0/m1 b yte 0 0 from the receive stm-0 soh processor block (b2 by te error count). 0 1 obtained from the contents of the transmit stm-0 section - m0/m1 byte value register (address location = 0x0737). 1 0 m0/m1 byte is obtained from the txsoh serial inpu t port. 1 1 from the receive stm-0 soh processor block (b2 by te error count).
preliminary XRT86SH221 192 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 2 - scramble enable this read/write bit-field is used to either enable or disable the scrambler, within the transmit stm-0 soh processor block circuitry. 0 - disables the scrambler. 1 - enables the scrambler. bit 1 - b2 byte error insert enable this read/write bit-field is used to configure the transmit stm-0 soh processor block to insert errors into the outbound b2 bytes, per the contents within the tran smit stm-0 section - transmit b2 byte error mask re gister. 0 - normal operation. 1 - configures the transmit stm-0 soh processor blo ck to insert into the b2 bytes (per the contents wi thin the transmit b2 byte error mask register). bit 0 - a1a2 byte error insert enable this read/write bit-field is used to configure the transmit stm-0 soh processor block to insert errors into the outbound a1 and a2 bytes, within the outbound stm-0 or stm-1 data-stream. 0 - normal operation. 1 - configures the transmit stm-0 soh processor blo ck to insert errors into the a1 and a2 bytes (per t he contents within the transmit a1 byte error mask and trans mit a2 byte error mask registers.
XRT86SH221 preliminary 193 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:1] - reserved bit 0 - stm-0 channel 0 - a1 byte error enable this read/write bit-field is used to configure the transmit stm-0 soh processor block to transmit a co ntinuous stream of stm-0 frames, in which the a1 byte is err ed by inverting the a1 byte to the value 0x09. 0 - normal operation 1 - configures the transmit stm-0 soh processor blo ck to transmit stm-0 frames with erred a1 bytes. n ote : this bit-field is only valid if bit-0 (a1a2 byte er ror insert), within the transmit stm-0 section C s dh transmit control register C byte 0 (address location= 0x0703 ) is set to 1. bit [7:1] - reserved bit 0 - stm-0 channel 0 - a2 byte error enable this read/write bit-field is used to configure the transmit stm-0 soh processor block to transmit a co ntinuous stream of stm-0 frames, in which the a2 byte is err ed by inverting the a2 byte to the value 0xd7. 0 - normal operation 1 - configures the transmit stm-0 soh processor blo ck to transmit stm-0 frames with erred a2 bytes. n ote : this bit-field is only valid if bit-0 (a1a2 byte er ror insert), within the transmit stm-0 section C s dh transmit control register C byte 0 (address location= 0x0703 ) is set to 1. t able 152: t ransmit stm-0 s ection a1 b yte e rror m ask (tsa1em 0 x 0717 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved stm-0 channel 0 a1 byte error enable ro ro ro ro ro ro ro r/w 0 0 0 0 0 0 0 0 t able 153: t ransmit stm-0 s ection a2 b yte e rror m ask (tsa2em 0 x 071f h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved stm-0 channel 0 a2 byte error enable ro ro ro ro ro ro ro r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 194 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - b1 byte error mask [7:0] these read/write bit-fields are used to insert bit errors into the b1 bytes, within the outbound stm-0 data stream. the transmit stm-0 soh processor block will perform an xor operation with the contents of the b1 byte, and this register. the results of this calculation will be i nserted into the b1 byte position within the outbou nd stm-0 data stream. for each bit-field (within this register) that is s et to 1, the corresponding bit, within the b1 byte will be in error. n ote : for normal operation, the user should set this regi ster to 0x00. bit [7:1] - reserved bit 0 - stm-0 channel 0 - b2 byte error enable this read/write bit-field is used to configure the transmit stm-0 soh processor block to perform the x or operation with the contents of the transmit stm-0 s ection -transmit b2 bit error mask register (addres s location = 0x072b) 0 - normal operation 1 - enables the xor operation. in this setting, the transmit stm-0 soh processor will perform the xor operation of the value of the b2 byte (within the outbound st m-0 frame) with the contents within the transmit st m-0 section - transmit b2 bit error mask register. n ote : this bit-field is only valid if bit 1 (b2 byte erro r insert), within the transmit stm-0 section C sdh transmit control register C byte 0 (address = 0x0703) set to 1. t able 154: t ransmit stm-0 s ection b1 b yte e rror m ask (tsb1em 0 x 0723 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 transmit b1 byte error mask [7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 155: t ransmit stm-0 s ection b2 b yte s elect e rror e nable (tsb2see 0 x 0727 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stm-0 channel 0 b2 byte error enable ro ro ro ro ro ro ro r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 195 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - transmit b2 byte error mask [7:0] these read/write bit-fields are used to insert b2 b yte errors into the outbound stm-0 data-stream, for diagnostic purposes. for the selected stm-0 channel (transmit b2 byte se lect error enable) within the transmit stm-0 sectio n - transmit b2 byte error register (address location = 0x0727) that is set to 1, then transmit stm-0 soh processor block will be configured to perform an xor operation between the contents of this register, with the contents of the selected stm-0 channel outbound b2 byte. the results of this calcu lation is written back into the b2 byte position, w ithin the outbound stm-0 frame. hence, for every bit (within this regi ster) that is set to 1, the corresponding bit (with in the outbound b2 byte) will be erred. n otes : 1. for normal (e.g., un-erred) operation, the user s hould ensure that this register is set to the value 0x00. 2. these register bits are ignored unless an stm-0 c hannel is selected (transmit b2 byte select error enable), within the transmit stm-0 section - transm it b2 byte error register has been set to "1". 3. this bit-field is only valid if bit 1 (b2 byte er ror insert), within the transmit stm-0 section C s dh transmit control register C byte 0 (address = 0x070 3) set to 1. t able 156: t ransmit stm-0 s ection b2 b yte e rror m ask (tsb2em 0 x 072b h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 transmit b2 byte error mask [7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 196 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - transmit k2 byte value if the appropriate k1k2 insert method is selected, then these read/write bit-fields are used to specif y the contents of the k2 byte, within the outbound stm-0 signal. n ote : if bit 1 (k1k2 insert method) within the transmit s tm-0 section - sdh transmit control register - byte 1 (address location= 0x0702) is set to 1, then the tr ansmit stm-0 soh processor block will load the cont ents of this register into the k2 byte-field, within each o utbound stm-0 frame. these register bits are ignore d if bit 1 (k1k2 insert method) is set to 0. bit [7:0] - transmit k1 byte value if the appropriate k1k2 insert method is selected, then these read/write bit-fields are used to specif y the contents of the k1 byte, within the outbound stm-0 signal. if bit 1 (k1k2 insert method) within the transmit s tm-0 section - sdh transmit control register - byte 1 (address location= 0x0702) is set to 1, then the transmit st m-0 soh processor block will load the contents of t his register into the k1 byte-field, within each outbound stm-0 frame. th ese register bits are ignored if bit 1 (k1k2 insert method) is set to 0. t able 157: t ransmit stm-0 s ection k2 b yte v alue r egister (tsk2vr 0 x 072e h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 transmit k2 byte value [7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 158: t ransmit stm-0 s ection k1 b yte v alue r egister (tsk1vr 0 x 072f h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 transmit k1 byte value [7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 197 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:4] - reserved bit 3 - external multiplex section remote defect in dicator enable this read/write bit-field is used to externally ins ert the value for bits 6, 7 and 8 (of the k2 byte) into the outbound stm-0 data stream. if the user enables this feature , then the user can enable or disable the insertion of the ms-rdi indicator, via the txsoh_n input pin. 0 - disables this feature. 1 - enables this feature. bit 2 - transmit multiplex section remote defect in dicator (ms-rdi) upon detection of ms-ais this read/write bit-field is used to configure the transmit stm-0 soh processor block to automatically transmit an ms-rdi indicator to the remote terminal anytime (an d for the duration) that the receive stm-0 soh proc essor block is detecting an multiplex section ais (ms-ais) indi cator. 0 - disables this feature. 1 - configures the transmit stm-0 soh processor blo ck to automatically transmit the ms-rdi indicator, upon the receive stm-0 soh processor block detecting the ms- ais indicator. bit 1 - transmit multiplex section remote defect in dicator (ms-rdi) upon detection of lof this read/write bit-field is used to configure the transmit stm-0 soh processor block to automatically transmit an ms-rdi indicator to the remote terminal anytime (an d for the duration) that the receive stm-0 soh proc essor block is declaring the lof defect. 0 - disables this feature. 1 -configures the transmit stm-0 soh processor bloc k to automatically transmit the ms-rdi indicator, w henever the receive stm-0 soh processor block declares the lof defect. bit 0 - transmit multiplex section remote defect in dicator (ms-rdi) upon detection of los this read/write bit-field is used to configure the transmit stm-0 soh processor block to automatically transmit an ms-rdi indicator to the remote terminal anytime (an d for the duration) that the receive stm-0 soh proc essor block is declaring the los defect. 0 - disables this feature. 1 -configures the transmit stm-0 soh processor bloc k to automatically transmit the ms-rdi indicator, w henever the receive stm-0 soh processor block declares the los defect. t able 159: t ransmit stm-0 s ection ms-rdi c ontrol r egister (tsmsrdicr 0 x 0733 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved external ms-rdi enable transmit ms-rdi upon ms-ais transmit ms-rdi upon lof transmit ms-rdi upon los ro ro ro ro r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 198 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - transmit m0m1 byte value if the appropriate m0m1 insert method is selected, then these read/write bit-fields are used to specif y the contents of the m0m1 byte, within the outbound stm-0 signal. n ote : if bit-0 (m0m1 insert method - bit 1) within the tr ansmit stm-0 section - sdh transmit control registe r - byte 1 (address location= 0x0702) and bit-7 (m0m1 byte i nsert method - bit 0) within the transmit stm-0 sec tion - sdh transmit control register - byte 0 (address l ocation= 0x0703) are set to 0, 1, then the stm-0 tr ansmit block will load the contents of this register into the m0m1 byte-field, within each outbound stm-0 fra me. these register bits are ignored if the m0m1 insert method [1:0] bits are set to any value other than 0, 1. bit [7:0] - transmit s1 byte value if the appropriate s1 insert method is selected, th en these read/write bit-fields are used to specify the contents of the s1 byte, within the outbound stm-0 signal. if bit 2 (s1 insert method) within the transmit stm-0 section - sdh transmit control register - byte 1 (address locatio n= 0x0702) is set to 1, then the stm-0 transmit blo ck will load the contents of this register into the s1 byte-field, w ithin each outbound stm-0 frame. n ote : these register bits are ignored if bit 2 (s1 insert method) is set to 0. bit [7:0] - transmit f1 byte value if the appropriate f1 byte insert method is selecte d, then these read/write bit-fields are used to spe cify the contents of the f1 byte, within the outbound stm-0 signal. n ote : if bit 3 (f1 byte insert method) within the transmi t stm-0 section - sdh transmit control register - b yte 1 (address location= 0x0702) is set to 1, then the tr ansmit stm-0 soh processor block will load the cont ents of this register into the f1 byte-field, within each o utbound stm-0 frame. these register bits are ignor ed if bit 3 (f1 insert method) is set to 0. t able 160: t ransmit stm-0 s ection m0m1 b yte v alue r egister (tsm0m1vr 0 x 0737 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 m0m1 byte value [7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 161: t ransmit stm-0 s ection - s1 b yte v alue r egister (tss1vr 0 x 073b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit s1 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 162: t ransmit stm-0 s ection - f1 b yte v alue r egister (tsf1vr 0 x 073f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit f1 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 199 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - transmit e1 byte value if the appropriate e1 byte insert method is selecte d, then these read/write bit-fields are used to spe cify the contents of the e1 byte, within the outbound stm-0 signal. note n ote : if bit 4 (e1 insert method) within the transmit stm -0 section - sdh transmit control register - byte 1 (address location= 0x0702) is set to 1, then the tr ansmit stm-0 soh processor block will load the cont ents of this register into the e1 byte-field, within each o utbound stm-0 frame. these register bits are ignor ed if bit 4 (e1 insert method) is set to 0. bit [7:0] - transmit e2 byte value if the appropriate e2 byte insert method is selecte d, then these read/write bit-fields are used to spe cify the contents of the e2 byte, within the outbound stm-0 signal. n ote : if bit 5 (e2 insert method) within the transmit stm -0 section - sdh transmit control register - byte 1 (address location= 0x0702) is set to 1, then the tr ansmit stm-0 soh processor block will load the cont ents of this register into the e2 byte-field, within each o utbound stm-0 frame. these register bits are ignor ed if bit 5 (e2 insert method) is set to 0. bit [7:0] - transmit j0 byte value these read/write bits are used to specify the value of the j0 byte, that will be transmitted via the t ransport overhead, within the very next stm-0 frame. this r egister is only valid if the transmit stm-0 soh pro cessor block is configured to read out the contents from this regis ter and insert it into the j0 byte-field within eac h outbound stm-0 frame. the user accomplishes this by setting bits 1 and 0 (j0_type), within the transmit stm-0 sectio n - j0 byte control register (address location= 0x074f) to 1, 0 . t able 163: t ransmit stm-0 s ection - e1 b yte v alue r egister (tse1vr 0 x 0743) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit e1 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 164: t ransmit stm-0 s ection - e2 b yte v alue r egister (tse2vr 0 x 0747) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit e2 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 165: t ransmit stm-0 s ection - j0 b yte v alue r egister (tsj0vr 0 x 074b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit j0 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 200 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:4] - unused bit [3:2] - message length[1:0] these two read/write bit-fields are used to specify the length of the message that is to be repetitive ly transmitted via the j0 byte as shown in the table below. j bit [1:0] - transmit j0 source[1:0] these two read/write bit-fields are used to specify the source of the message that will be transported via the j0 byte/ message, within the outbound stm-0 data-stream, as shown in the table below t able 166: t ransmit stm-0 s ection - t ransmitter j0 b yte c ontrol r egister (tsj0cr 0 x 074f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused message length[1:0] j0 type[1:0] r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 message length msg_length[1:0] c orresponding m essage l ength (b ytes ) 00 1 byte 01 16 bytes 10 or 11 64 bytes source of j0 byte message j0_type [1:0] c orresponding s ource of j0 b yte /m essage . 00 automatically set the j0 byte, in each outbound s tm-0 frame to 0x01. 01 the transmit section tracemessage bufferthe trans mit stm-0 section trace buffer mem- ory is located at address locations 0x0900 through 0x093f. 10 from the transmit j0 byte value[7:0] register. in this setting, the transmit stm-0 soh pro- cessor block will read out the contents of the tran smit j0 value[7:0] register (address loca- tion= 0x074b), and will insert this value into the j0 byte of each outbound stm-0 frame. 11 from the txsoh_n input pin.
XRT86SH221 preliminary 201 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 6.7 transmit path overhead processor block registers the register map for the transmit stm-0 poh process or block is presented in the table below. addition ally, a detailed description of each of the transmit stm-0 poh processor block registers is presented below. i bit [7:2] - unused bit [1:0] - payload type[1:0] this read/write bit-field is used to configure the device for the type of vc-3 payload the device will be carrying. 00 - lte (input poh and fixed stuffing). 01 - asynchronous e1 mapping. 10 - reserved 11 - reserved t able 167: t ransmit stm-0 p ath c ontrol r egister - b yte 2 (tpcr2 0 x 0781) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused payload type[1:0] r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 202 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:4] - unused bit 3 - z5 insertion type this read/write bit-field is used to configure the transmit stm-0 poh processor block to use either th e transmit stm-0 path - transmit z5 value register or the tpoh input pin as the source for the z5 byte, in the ou tbound vc-3. 0 - configures the transmit stm-0 poh processor blo ck to use the transmit stm-0 path - transmit z5 val ue register (address location= 0x07b3). 1 - configures the transmit stm-0 poh processor blo ck to use the tpoh input as the source for the z5 b yte, in the outbound vc-3. bit 2 - z4 insertion type this read/write bit-field is used to configure the transmit stm-0 poh processor block to use either th e transmit stm-0 path - transmit z4 value register or the tpoh input pin as the source for the z4 byte, in the ou tbound vc-3. 0 - configures the transmit stm-0 poh processor blo ck to use the transmit stm-0 path - transmit z4 val ue register (address location= 0x07af). 1 - configures the transmit stm-0 poh processor blo ck to use the tpoh input as the source for the z4 b yte, in the outbound vc-3. bit 1 - z3 insertion type this read/write bit-field is used to configure the transmit stm-0 poh processor block to use either th e transmit stm-0 path - transmit z3 value register or the tpoh input pin as the source for the z3 byte, in the ou tbound vc-3. 0 - configures the transmit stm-0 poh processor blo ck to use the transmit stm-0 path - transmit z3 val ue register (address location = 0x07ab). 1 - configures the transmit stm-0 poh processor blo ck to use the tpoh input as the source for the z3 b yte, in the outbound vc-3. bit 0 - h4 insertion type this read/write bit-field is used to configure the transmit stm-0 poh processor block to use either th e transmit stm-0 path - transmit h4 value register or the tpoh input pin as the source for the h4 byte, in the ou tbound vc-3. 0 - configures the transmit stm-0 poh processor blo ck to use the transmit stm-0 path - transmit h4 val ue register (address location= 0x07a7). 1 - configures the transmit stm-0 poh processor blo ck to use the tpoh input as the source for the h4 b yte, in the outbound vc-3. t able 168: t ransmit stm-0 p ath c ontrol r egister - b yte 1 (tpcr1 0 x 0782) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused z5 insertion type z4 insertion type z3 insertion type h4 insertion type r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 203 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - f2 insertion type this read/write bit-field is used to configure the transmit stm-0 poh processor block to use either th e transmit stm-0 path - transmit f2 value register or the tpoh input pin as the source for the f2 byte, in the ou tbound vc-3. 0 - configures the transmit stm-0 poh processor blo ck to use the transmit stm-0 path - transmit f2 val ue register (address location= 0x07a3). 1 - configures the transmit stm-0 poh processor blo ck to use the tpoh input as the source for the f2 b yte, in the outbound vc-3. bit [6:5] - high order path remote error indication (hp-rei) insertion type[1:0] these two read/write bit-fields are used to configu re the transmit stm-0 poh processor block to use on e of the three following sources for the hp-rei bit-fields ( e.g., bit-7 through -4, within the g1 byte of the o utbound vc-3). ? from the corresponding receive stm-0 poh processor block (e g., when it detects b3 bytes in its incomi ng vc-3 data). ? from the transmit g1 byte value register (address l ocation= 0x079f). ? from the tpoh input pin. 00/11 - configures the transmit stm-0 poh processor block to set bits-7 through -4 (in the g1 byte of the outbound vc-3) based upon receive conditions as detected by the corresponding receive stm-0 poh processor block . 01 - configures the transmit stm-0 poh processor bl ock to set bits-7 through -4 (in the g1 byte of the outbound vc-3) based upon the contents within the transmit g 1 byte value register (address location= 0x079f). 10 - configures the transmit stm-0 poh processor bl ock to use the tpoh input pin as the source of bits 1 through 4 (in the g1 byte of the outbound vc-3). bit [4:3] - high order path remote defect indicator (hp-rdi) insertion type[1:0] these two read/write bit-fields are used to configu re the transmit stm-0 poh processor block to use on e of the three following sources for the hp-rdi bit-fields ( e.g., bits-3 through -1, within the g1 byte of the outbound vc-3). ? from the receive stm-0 poh processor block (e g., w hen it detects various alarm conditions within its incoming vc-3 data). ? from the transmit g1 byte value register (address l ocation = 0x079f). ? from the tpoh input pin. 00/11 - configures the transmit stm-0 poh processor block to set bits-3 through -1 (in the g1 byte of the outbound vc-3) based upon receive conditions as detected by the receive stm-0 poh processor block. 01 - configures the transmit stm-0 poh processor bl ock to set bits-3 through -1 (in the g1 byte of the outbound vc-3) based upon the contents within the transmit g 1 byte value register. 10 - configures the transmit stm-0 poh processor bl ock to use the tpoh input pin as the source of bits 5 through 7 (in the g1 byte of the outbound vc-3). bit 2 - c2 insertion type this read/write bit-field is used to configure the transmit stm-0 poh processor block to use either th e transmit stm-0 path - transmit c2 byte value register or the tpoh input pin as the source for the c2 byte, in t he outbound vc-3. 0 - configures the transmit stm-0 poh processor blo ck to use the transmit stm-0 path - transmit c2 val ue register (address location= 0x079b). 1 - configures the transmit stm-0 poh processor blo ck to use the tpoh input as the source for the c2 b yte, in the t able 169: t ransmit stm-0 p ath c ontrol r egister - b yte 0 (tpcr0 0 x 0783) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f2 insertion type hp-rei insertion type[1:0] hp-rdi insertion type[1:0 ] c2 byte insertion type c2 byte auto insert mode enable transmit au-ais enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 204 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu outbound vc-3. bit 1 - auto-insert hp-pdi indicator enable this read/write bit-field are used to configure the transmit stm-0 poh processor block to automaticall y insert the hp-pdi (path - payload defect indicator) whenever t he au-ais indicator is received from the receive so net poh processor block. if this feature is enabled, then the transmit stm-0 poh processor block will automatically set the c2 byte (within the outbound vc-3) to 0xfc (to indicate a hp-pdi condit ion) whenever it receives the au-ais indicator, fro m the receive sonet poh processor block. bit 0 - transmit au-ais enable this read/write bit-field is used to configure the transmit stm-0 poh processor block to (via software control) transmit an au-ais indicator to the remote pte. if this feature is enabled, then the transmit stm-0 po h processor block will automatically set the h1, h2, h3 and all the vc-3 bytes to an all ones pattern, prior to ro uting this data to the transmit stm-0 toh processor block. 0 - configures the transmit stm-0 poh processor blo ck to not transmit the au-ais indicator to the remo te pte. 1 - configures the transmit stm-0 poh processor blo ck to transmit the au-ais indicator to the remote p te.
XRT86SH221 preliminary 205 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - transmit j1 byte value these read/write bit-fields are used to have softwa re control over the value of the j1 byte, within ea ch outbound vc-3. if the user configures the transmit stm-0 poh proc essor block to this register as the source of the j 1 byte, then it will automatically write the contents of this register i nto the j1 byte location, within each outbound vc-3 . this feature is enabled whenever the user writes a 0 into bit 2 (c2 insertion type) within the transmi t stm-0 path - j1 control register register (address location= 0x0 783). bit [7:0] - transmit b3 byte mask[7:0] this read/write bit-field is used to insert errors into the b3 byte, within the outbound vc-3, prior t o transmission to the transmit stm-0 toh processor block. the transmit stm-0 poh processor block will perform an xor operation with the contents of this registe r, and the b3 byte value. the results of this operation will be written back into the b3 byte of the outbound vc-3. n ote : if the user sets a particular bit-field, within thi s register, to 1, then that corresponding bit, with in the outbound b3 byte will be in error. for normal operation, the u ser should set this register to 0x00. bit [7:0] - transmit c2 byte value these read/write bit-fields are used to have softwa re control over the value of the c2 byte, within ea ch outbound vc-3. if the user configures the transmit stm-0 poh proce ssor block to this register as the source of the c2 byte, then it will automatically write the contents of this register i nto the c2 byte location, within each outbound vc-3 . this feature is enabled whenever the user writes a 0 into bit 2 (c2 byte insertion type) within the tr ansmit stm-0 path - sonet control register - byte 0 register (address location= 0x0783). t able 170: t ransmit stm-0 p ath j1 b yte v alue r egister (tpj1vr 0 x 0793) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit j1 byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 171: t ransmit stm-0 p ath b3 b yte e rror m ask r egister (tpb3em 0 x 0797) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit b3 byte mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 172: t ransmit stm-0 p ath c2 b yte v alue r egister (tpc2vr 0 x 079b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit c2 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 206 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - transmit g1 byte value: these read/write bit-fields are used to have softwa re control over the contents of the hp-rdi and hp-r ei bit-fields, within each g1 byte in the outbound vc-3. n ote : if the users sets hp-rei insertion type[1:0] and hp -rdi insertion type[1:0] bits to the value [0, 1], then contents of the hp-rei and the hp-rdi bit-fields (w ithin each g1 byte of the outbound vc-3) will be di ctated by the contents of this register. the hp-rei insertio n type[1:0] and hp-rdi insertion type[1:0] bit-fiel ds are located in the transmit stm-0 path - sonet control register - byte 0 register (address location= 0x078 3) bit [7:0] - transmit f2 byte value these read/write bit-fields are used to have softwa re control over the value of the f2 byte, within ea ch outbound vc-3. if the user configures the transmit stm-0 poh proce ssor block to this register as the source of the f2 byte, then it will automatically write the contents of this register i nto the f2 byte location, within each outbound vc-3 . this feature is enabled whenever the user writes a 0 into bit7 (f2 byte insertion type) within the tra nsmit stm-0 path - sonet control register - byte 0 register (address location= 0x0783). bit [7:0] - transmit h4 byte value these read/write bit-fields are used to have softwa re control over the value of the h4 byte, within ea ch outbound vc-3. if the user configures the transmit stm-0 poh proce ssor block to this register as the source of the h4 byte, then it will automatically write the contents of this register i nto the h4 byte location, within each outbound vc-3 . this feature is enabled whenever the user writes a 0 into bit 0 (h4 insertion type) within the transmi t stm-0 path - sonet control register - byte 1 register (address l ocation= 0x07a7). t able 173: t ransmit stm-0 p ath g1 b yte v alue r egister (tpg1vr 0 x 079f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit g1 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 174: t ransmit stm-0 p ath f2 b yte v alue r egister (tpf2vr 0 x 07a3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit f2 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 175: t ransmit stm-0 p ath h4 b yte v alue r egister (tph4vr 0 x 07a7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit h4 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 207 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - transmit z3 byte value these read/write bit-fields are used to have softwa re control over the value of the z3 byte, within ea ch outbound vc-3. if the user configures the transmit stm-0 poh processor block to this register as the source of the z3 byte, then it will automatically write the contents of this re gister into the z3 byte location, within each outbo und vc-3. this feature is enabled whenever the user writes a 0 into bit 1 (z3 insertion type) within the transmi t stm-0 path - sonet control register - byte 0 register (address l ocation= 0x0782). bit [7:0] - transmit z4 byte value these read/write bit-fields are used to have softwa re control over the value of the z4 byte, within ea ch outbound vc-3. if the user configures the transmit stm-0 poh proce ssor block to this register as the source of the z4 byte, then it will automatically write the contents of this register i nto the z4 byte location, within each outbound vc-3 . this feature is enabled whenever the user writes a 0 into bit 2 (z4 insertion type) within the transmi t stm-0 path - sonet control register - byte 0 register (address l ocation= 0x0782). bit [7:0] - transmit z5 byte value these read/write bit-fields are used to have softwa re control over the value of the z5 byte, within ea ch outbound vc-3. if the user configures the transmit stm-0 poh proce ssor block to this register as the source of the z5 byte, then it will automatically write the contents of this register i nto the z5 byte location, within each outbound vc-3 . this feature is enabled whenever the user writes a 0 into bit 3 (z5 insertion type) within the transmi t stm-0 path - sonet control register - byte 0 register (address l ocation= 0x0782). t able 176: t ransmit stm-0 p ath z3 b yte v alue r egister (tpz3vr 0 x 07ab) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit z3 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 177: t ransmit stm-0 p ath z4 b yte v alue r egister (tpz4vr 0 x n9af) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit z4 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 178: t ransmit stm-0 p ath z5 b yte v alue r egister (tpz5vr 0 x 07b3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit z5 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 208 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - unused bitt 5 - pointer force this read/write bit-field is used to load the value s contained within the transmit stm-0 poh arbitrary h1 pointer and transmit stm-0 poh arbitrary h2 pointer registe rs (address location= 0x07bf and 0x07c3) into the h 1 and h2 bytes (within the outbound stm-0 data stream). the actual location of the vc-3 will not be adjuste d, per the value of h1 and h2 bytes. hence, this f eature should cause the remote terminal to declare an invalid poi nter condition. 0 - configures the transmit stm-0 poh and toh proce ssors to transmit stm-0 data will normal and correc t h1 and h2 bytes. 1 - configures the transmit stm-0 poh and toh proce ssor blocks to overwrite the values of the h1 and h 2 bytes (in the outbound stm-0 data-stream) with the values in the transmit stm-0 poh arbitrary h1 and h2 poin ter registers. bitt 4 - check stuff monitoring this read/write bit-field is used to configure the transmit stm-0 poh and toh processor blocks to only execute a positive, negative or ndf event (via the insert p ositive stuff, insert negative stuff, insert contin uous or single ndf options, via software command) if no pointer adjust ment (ndf or otherwise) has occurred during the las t 3 stm-0 frame periods. 0 - disables this feature.in this mode, the transmi t stm-0 poh and toh processor block will execute a software- commanded pointer adjustment event, independent of whether a pointer adjustment event has occurred in the last 3 stm-0 frame periods. 1 - enables this feature.in this mode, the transmit stm-0 poh and toh processor block will only execut e a software-commanded pointer adjustment event, if no pointer adjustment event has occurred during the la st 3 stm-0 frame periods. bitt 3 - insert negative stuf this read/write bit-field is used to configure the transmit stm-0 poh and toh processor blocks to inse rt a negative-stuff into the outbound stm-0 data stream. this command, in-turn will cause a pointer decrem enting event at the remote terminal. writing a 0 to 1 transition into this bit-field ca uses the following to happen. ? a negative-stuff will occur (e.g., a single payload byte will be inserted into the h3 byte position wi thin the outbound stm-0 data stream). ? the d bits, within the h1 and h2 bytes will be inve rted (to denote a decrementing pointer adjustment e vent). ? the contents of the h1 and h2 bytes will be decreme nted by 1, and will be used as the new pointer from this point on. n ote : once the user writes a 1 into this bit-field, the x rt86sh328 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to 0. bitt 2 - insert positive stuff this read/write bit-field is used to configure the transmit stm-0 poh and toh processor blocks to inse rt a positive-stuff into the outbound stm-0 data stream. this command, in-turn will cause a pointer increm enting event at the remote terminal. writing a 0 to 1 transition into this bit-field ca uses the following to happen. t able 179: t ransmit stm-0 p ath p ointer c ontrol r egister (tppcr 0 x 07b7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused pointer force check stuff insert negative stuff insert positive stuff insert continuous ndf events insert single ndf event r/o r/o r/w r/w w w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 209 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 ? a positive-stuff will occur (e.g., a single stuff-b yte will be inserted into the stm-0 data-stream, im mediately after the h3 byte position within the outbound stm- 0 data stream). ? the i bits, within the h1 and h2 bytes will be inve rted (to denote a incrementing pointer adjustment e vent). ? the contents of the h1 and h2 bytes will be increme nted by 1, and will be used as the new pointer from this point on.note n ote : once the user writes a 1 into this bit-field, the x rt86sh328 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to 0. bitt 1 - insert continuous ndf events this read/write bit-field is used configure the tra nsmit stm-0 poh and toh processor blocks to continu ously insert a new data flag (ndf) pointer adjustment int o the outbound stm-0 data stream. as the transmit stm-0 poh and toh processor blocks insert the ndf event into the stm-0 data stream, it will proceed to load in the contents of the transmit stm -0 poh arbitrary h1 pointer and transmit stm-0 poh arbitrary h2 pointer registers into the h1 and h2 bytes (with in the outbound stm-0 data stream). 0 - configures the transmit stm-0 toh and poh proce ssor blocks to not continuously insert ndf events i nto the outbound stm-0 data stream. 1- configures the transmit stm-0 toh and poh proces sor blocks to continuously insert ndf events into t he outbound stm-0 data stream. bitt 0 - insert single ndf event this read/write bit-field is used to configure the transmit stm-0 poh and toh processor blocks to inse rt a new data flag (ndf) pointer adjustment into the outboun d stm-0 data stream. writing a 0 to 1 transition into this bit-field cau ses the following to happen ? the n bits, within the h1 byte will set to the valu e 1001 ? the ten pointer-value bits (within the h1 and h2 by tes) will be set to new pointer value per the conte nts within the transmit stm-0 poh - arbitrary h1 pointer and t ransmit stm-0 poh arbitrary h2 pointer registers (address location= 0x07bf and 0xn9c3). n ote : afterwards, the n bits will resume their normal val ue of 0110 and this new pointer value will be used as the new pointer from this point on. once the user writes a 1 into this bit-field, the xrt86sh328 will automati cally clear this bit-field. hence, there is no need to subsequ ently reset this bit-field to 0.
preliminary XRT86SH221 210 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:2] - unused bit [1:0] - j1 byte insertion_method[1:0] these read/write bit-fields are used to specify the method that the user will use to insert the j1 byt e into the outbound vc-3. the relationship between the conten ts of these bit-fields and the corresponding j1 byt e insertion method is presented below. bit [7:4] - ndf (new data flag) bits these read/write bit-fields are used provide the va lue that will be loaded into the ndf bit-field (of the h1 byte), whenever a 0 to 1 transition occurs in bit 5 (point er force) within the transmit stm-0 path - transmit path control register (address location= 0x07b7). bit [3:2] - ss bits these read/write bit-fields is used to provide the value that will be loaded into the ss bit-fields (o f the h1 byte) whenever a 0 to 1 transition occurs in bit 5 (poin ter force) within the transmit stm-0 path - transmi t path control register (address location= 0x07b7). the ss bits have no functional value, within the h1 byte. bit [1:0] - h1 pointer value[1:0] these two read/write bit-fields, along with the con stants of the transmit stm-0 path - transmit arbitr ary h2 pointer register (address location= 0x07c3) are used to pro vide the contents of the pointer word. these two read/write bit-fields are used to define the value of the two most significant bits within t he pointer word. whenever a 0 to 1 transition occurs in bit 5 (point er force) within the transmit stm-0 path - transmit path control register (address location= 0x07b7), the values of these two bits will be loaded into the two most sig nificant bits within the pointer word. t able 180: t ransmit stm-0 p ath j1 c ontrol r egister (tpj1cr 0 x 07bb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused insertion method[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 insertion method j1 b yte i nsertion m ethod [1:0] r esulting i nsertion m ethod 00 insert the value 0x00 01 not valid 10 insert from the transmit sonet path - transmit j1 byte value register (address location= 0x0793) 11 insert via the txpoh_n input port t able 181: t ransmit stm-0 p ath a rbitrary h1 p ointer r egister (tph1pr 0 x 07bf) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ndf bits ss bits h1 pointer value r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 211 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - h2 pointer value[1:0] these eight read/write bit-fields, along with the c onstants of bits 1 and 0 within the transmit stm-0 path - transmit arbitrary h1 pointer register (address location= 0x 07c3) are used to provide the contents of the point er word. these two read/write bit-fields are used to define the va lue of the eight least significant bits within the pointer word. whenever a 0 to 1 transition occurs in bit 5 (point er force) within the transmit stm-0 path - transmit path control register (address location= 0x07b7), the values of these eight bits will be loaded into the h2 byte, w ithin the outbound stm-0 data stream. bit [7:2] - unused bit [1:0] - transmit pointer word - high[1:0] these two read-only bits, along with the contents o f the transmit stm-0 path - transmit current pointe r byte register - byte 0 (address location= 0x07c7) reflec t the current value of the pointer (or offset of vc -3 within the stm- 0 frame). these two bits contain the two most sign ificant bits within the 10-bit pointer word. bit [7:0] - transmit pointer word - low[7:0] these two read-only bits, along with the contents o f the transmit stm-0 path - transmit current pointe r byte register - byte 1 (address location= 0x07c6) reflec t the current value of the pointer (or offset of vc -3 within the stm- 0 frame). these two bits contain the eight least s ignificant bits within the 10-bit pointer word. t able 182: t ransmit stm-0 p ath a rbitrary h2 p ointer r egister (tph2pr 0 x 07c3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h2 pointer value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 183: t ransmit stm-0 p ath c urrent p ointer b yte r egister - b yte 1 (tpcpr1 0 x 07c6) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused tx pointer high[1:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 1 0 t able 184: t ransmit stm-0 p ath c urrent p ointer b yte r egister - b yte 0 (tpcpr0 0 x 07c7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx pointer low[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 1 0 1 0
preliminary XRT86SH221 212 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:4] - unused bit [3:1] - hp-plm (high order path - payload misma tch) - hp-rdi code these three read/write bit-fields are used to speci fy the value that the transmit stm-0 poh processor block will transmit, within the hp-rdi bit-fields of the g1 by te (within the outbound vc-3), whenever the corresp onding receive stm-0 poh processor block detects and declares a hp -plm condition. in order to enable this feature, t he user must set bit 0 (hp-rdi upon hp-plm) within this register to 1. bit 0 - transmit hp-rdi upon hp-plm this read/write bit-field is used to configure the transmit stm-0 poh processor block to automatically transmit the hp-rdi code (as configured in bits 3 through 1 - wi thin this register) whenever the corresponding rece ive stm-0 poh processor block declares a hp-plm condition. 0 - disables the automatic transmission of hp-rdi u pon detection of hp-plm. 1 - enables the automatic transmission of hp-rdi up on detection of hp-plm. t able 185: t ransmit stm-0 p ath hp-rdi c ontrol r egister - b yte 2 (tphp-rdicr2 0 x 07c9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused hp-plm hp-rdi code[2:0] transmit hp-rdi upon hp-plm r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 213 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:5] - hp-tim (high order path - trace identif ication message mismatch) - hp-rdi code these three read/write bit-fields are used to speci fy the value that the transmit stm-0 poh processor block will transmit within the hp-rdi bit-fields of the g1 byt e (within the outbound vc-3), whenever the receive stm-0 poh processor block detects and declares the hp-tim def ect condition. to enable this feature, the user must set bit 4 (tr ansmit hp-rdi upon hp-tim) within this register to 1. bit 4 - transmit hp-rdi upon hp-tim this read/write bit-field is used to configure the transmit stm-0 poh processor block to automatically transmit the hp-rdi code (as configured in bits 7 through 5 - wi thin this register) whenever the corresponding rece ive stm-0 poh processor block declares the hp-tim defect conditio n. 0 - disables the automatic transmission of hp-rdi u pon detection of hp-tim. 1 - enables the automatic transmission of hp-rdi up on detection of hp-tim. bit [3:1] - hp-uneq (high order path - unequipped) - hp-rdi code these three read/write bit-fields are used to speci fy the value that the transmit stm-0 poh processor block will transmit, within the hp-rdi bit-fields of the g1 by te (within the outbound vc-3), whenever the receive stm-0 poh processor block detects and declares the hp-uneq de fect condition. to enable this feature, the user must set bit 0 (tr ansmit hp-rdi upon hp-uneq) within this register to 1. bit 0 - transmit hp-rdi upon hp-uneq this read/write bit-field is used to configure the transmit stm-0 poh processor block to automatically transmit the hp-rdi code (as configured in bits 3 through 1 - wi thin this register) whenever the corresponding rece ive stm-0 poh processor block declares the hp-uneq defect conditi on. 0 - disables the automatic transmission of hp-rdi u pon detection of hp-uneq. 1 - enables the automatic transmission of hp-rdi up on detection of hp-uneq. t able 186: t ransmit stm-0 p ath hp-rdi c ontrol r egister - b yte 1 (tphp-rdicr1 0 x 07ca) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hp-tim hp-rdi code[2:0] transmit hp-rdi upon hp-tim hp-uneq hp-rdi code[2:0] transmit hp-rdi upon hp-uneq r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 214 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:5] - au-lop (administrative unit - loss of p ointer) - hp-rdi code these three read/write bit-fields are used to speci fy the value that the transmit stm-0 poh processor block will transmit, within the hp-rdi bit-fields of the g1 by te (within the outbound vc-3), whenever the corresp onding receive stm-0 poh processor block detects and declares a au -lop condition. to enable this feature, the user must set bit 4 (hp -rdi upon au-lop) within this register to 1. bit 4 - transmit hp-rdi upon au-lop this read/write bit-field is used to configure the transmit stm-0 poh processor block to automatically transmit the hp-rdi code (as configured in bits 7 through 5 - wi thin this register) whenever the corresponding rece ive stm-0 poh processor block declares a au-lop condition 0 - disables the automatic transmission of hp-rdi upon detection of au-lop. 1 - enables the automatic transmission of hp-rdi up on detection of au-lop. bit[3:1]au-ais (administrative unit - alarm indicat ion signal) - hp-rdi code these three read/write bit-fields are used to speci fy the value that the transmit stm-0 poh processor block will transmit, within the hp-rdi bit-fields of the g1 by te (within the outbound vc-3), whenever the corresp onding receive stm-0 poh processor block detects and declares an a u-ais condition. to enable this feature, the user must set bit 4 (hp -rdi upon au-ais) within this register to 1. bit 0 - transmit hp-rdi upon au-ais this read/write bit-field is used to configure the transmit stm-0 poh processor block to automatically transmit the hp-rdi code (as configured in bits 7 through 5 - wi thin this register) whenever the corresponding rece ive stm-0 poh processor block declares a au-ais condition. 0 - disables the automatic transmission of hp-rdi u pon detection of au-ais. 1 - enables the automatic transmission of hp-rdi up on detection of au-ais. bit [7:4] - unused bit 3:0] - txpohclk output clock signal speed these read/write bit-fields are used to specify the frequency of the txpohclk output clock signal. the formula that relates the contents of these register bits to the txpohclk frequency is presented below. freq = 51.84 /[2 * (txpoh_clock_speed + 1) for stm-1 applications, the frequency of the rxpohc lk output signal must be in the range of 2.36mhz to 25.92mhz t able 187: t ransmit stm-0 p ath hp-rdi c ontrol r egister - b yte 0 (tphp-rdicr0 0 x 07cb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 au-lop hp-rdi code[2:0] transmit hp-rdi upon au-lop au-ais hp-rdi code[2:0] transmit hp-rdi upon au-ais r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 188: t ransmit stm-0 p ath s erial p ort c ontrol r egister (tpspcr 0 x 07cf) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused txpoh clock speed[4:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 215 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 6.8 global e1 line interface unit register descripti ons (liu) bit 7 - reserved bit 6 - automatic all ones generation upon rlos con dition this bit will force an unframed all ones signal to the egress tx liu line interface whenever its corre sponding ingress rx liu input experiences an rlos condition. 0 - disabled 1 - enable ataos bit [5:2] - reserved bit 1 - transmit clock control this bit is used to set the transmitter activity in the event that the transmit clock is missing. 0 - send all zeros to the line 1 - send all ones to the line bit 0 - software reset of liu blocks only this bit grants permission to reset all internal ci rcuits to their default state. this bit does not re set the register values. 0 - normal operation 1 - liu software reset t able 189: g lobal l ine i nterface c ontrol r egister 5 (glicr5 0 x 0100 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved ataos reserved tclkcntl liusrst r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 216 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - line code violation / over flow monitoring select this bit is used to select the monitoring function of the lcv_of alarm in the liu interrupt block. 0 - monitors lcv errors 1 - monitors the over flow status of the lcv counte r bit [6:3] - reserved bit 2 - receive mute upon rlos this bit forces all zeros on the ingress path to pr event data chattering whenever the rx liu line inte rface experiences an rlos condition. 0 - disabled 1 - rxmute enabled bit 1 - extended loss of signal this bit is used to extend the time period to 4,096 recovered line clocks before declaring/clearing rl os on the ingress path. 0 - normal rlos declaration/clearance 1 - exlos enabled bit 0 - in circuit testing this bit forces all ingress and egress signals to b e high-z. 0 - disabled 1 - enabled bit [7:2] - reserved bit [1:0] - master clock select these bits configure the input reference clock to t he low speed interface blocks. 00 - 2.048mhz input clock reference 01 = 4.096mhz input clock reference 10 - 8.192 mhz input clock reference 11 = 16.384mhz input clock reference t able 190: g lobal l ine i nterface c ontrol r egister 4 (glicr4 0 x 0101 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lcv_ofsel reserved rxmute exlos ict r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 191: g lobal l ine i nterface c ontrol r egister 3 (glicr3 0 x 0102 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved mclksel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 217 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [6:0] - global channel interrupt status for the liu blocks bit [6:0] - global channel interrupt status for the liu blocks bit [6:0] - global channel interrupt status for the liu blocks t able 192: g lobal l ine i nterface c ontrol r egister 2 (glicr2 0 x 0103 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved gchis[6:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 193: g lobal l ine i nterface c ontrol r egister 1 (glicr1 0 x 0104 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved gchis[13:7] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 194: g lobal l ine i nterface c ontrol r egister 0 (glicr0 0 x 0105 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved gchis[20:14] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 218 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 6.9 individual channel e1 line interface unit regist er descriptions (liu) bit 7 - prbs/qrss select this bit is used to select the type of diagnostic p attern. 0 - prbs 1 - qrss bit 6 - random bit sequence direction select this bit selects which direction the diagnostic pat tern will be sent. 0 - egress (ttip/tring) 1 - ingress (toward the vt mapper block) bit 5 - receiver on select this bit is used to turn the receiver on of off. 0 - off 1 - on bit [4:0] - reserved t able 195: c hannel l ine i nterface c ontrol r egister 9 (clicr9 0 x n000 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 prbs_qrss prbs_tx_rx rxon reserved r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 219 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - receive termination select this bit is used to select between the internal rec eive termination (line impedance) and high-z. 0 - high-z 1 - internal termination bit 6 - transmit termination select this bit is used to select between the internal tra nsmit termination (line impedance) and high-z. 0 - high-z 1 - internal impedance bit 5 - this bit must be set to 0 at all times bit 4 - transmit and receive termination select this bit sets the termination impedance for both th e liu receiver and transmitter. 0 - 75 w 1 - 120 w bit [3:2] - jitter attenuator select this bit is used to enable the receive jitter atten uator. 00 - disabled 01 - transmit path 10 - receive path 11 - receive path bit 1 - jitter bandwidth select this bit is used to select the band width of the re ceive and transmit jitter attenuators. 0 - 10 hz 1 - 1.5 hz bit 0 - fifo depth select this bit is used to select the depth of the fifo wi thin both the receive and transmit jitter attenuato rs. 0 - 32-bit fifo 1 - 64-bit fifo t able 196: c hannel l ine i nterface c ontrol r egister 8 (clicr8 0 x n001 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rxtsel txtsel force to 0 tersel jasel[1:0] jbwsel fifosel r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 220 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - invert prbs/qrss pattern this bit is used to invert the pattern chosen in re gister clicr0 and if enabled in txtest[2:0] bits be low. 0 - normal pattern 1 - pattern inversion enabled bit [6:4] - transmit test pattern select these bits are used to select diagnostic test patte rn to be enabled to the egress liu block. 0xx - reserved 100 - prbs/qrss pattern 101 - taos 11x - reserved bit 3 - transmitter enable this bit is used to enable the transmitter output. 0 - disabled 1 - enabled bit [2:0] - diagnostic loop back test enable these bits are used to enable the various loop back modes supported in the liu block. 0xx - no loop back 100 - dual loop back enabled 101 - analog loop back enabled 110 - remote loop back enabled 111 - digital loop back enabled t able 197: c hannel l ine i nterface c ontrol r egister 7 (clicr7 0 x n002 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 invprbs txtest[2:0] txon loop[2:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 221 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:3] - reserved bit 2 - insert bipolar violation this bit is used to force one bipolar violation err or in the egress transmit direction. this feature i s enabled by the transition of a 0 to 1. 0 - disabled (idle state) 1 - force one bipolar violation bit 1 - insert bit error this bit is used to force one bit error in the egre ss transmit direction. this feature is enabled by t he transition of a 0 to 1. 0 - disabled (idle state) 1 - force one bit error bit 0 - reserved t able 198: c hannel l ine i nterface c ontrol r egister 6 (clicr6 0 x n003 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved insbpv insber reserved r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 222 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - reserved bit 6 - digital monitor output interrupt enable 0 - disabled 1 - interrupt enabled bit 5 - fifo limit status interrupt enable 0 - disabled 1 - interrupt enabled bit 4 - line code violation / over flow interrupt e nable 0 - disabled 1 - interrupt enabled bit 3 - reserved bit 2 - alarm indication signal interrupt enable 0 - disabled 1 - interrupt enabled bit 1 - receive loss of signal interrupt enable 0 - disabled 1 - interrupt enabled bit 0 - prbs / qrss random pattern interrupt enable 0 - disabled 1 - interrupt enabled t able 199: c hannel l ine i nterface c ontrol r egister 5 (clicr5 0 x n004 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved dmoie flsie lcv_ofie reserved aisie rlosie qrpie r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 223 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - reserved bit 6 - digital monitor output detection this bit field monitors the dmo function and will b e set to 1 if there is no activity present on the t ransmitter outputs for 128 consecutive clock cycles. at all other times, t his bit will be set to 0. 0 - no alarm 1 - alarm detected bit 5 - fifo limit status detection this bit field monitors the fifo and will be set to 1 if the read and write pointers are with +/- 3bit s. at all other times, this bit will be set to 0. 0 - no alarm 1 - alarm detected bit 4 - line code violation / over flow detection this bit field monitors the lcv function on the rec eiver inputs and will be set to 1 if either (a) a l ine code violation occurs, or (b) the lcv counter is full. this is dependent o n bit 7 in glicr1. 0 - no alarm 1 - alarm detected bit 3 - reserved bit 2 - alarm indication signal detection this bit field monitors the ais function on the rec eiver inputs and will be set to 1 if an alarm indic ation signal is detected according to itu-t g.775 specifications. 0 - no alarm 1 - alarm detected bit 1 - receive loss of signal detection this bit field monitors the rlos function on the re ceiver inputs and will be set to 1 if a receiver lo ss of signal occurs according to either itu-t g.775 or etsi-300-233. 0 - no alarm 1 - alarm detected bit 0 - prbs / qrss random pattern detection this bit field monitors the prbs/qrss function on t he receiver inputs and will be set to 1 if the chos en pattern in register clicr0 is detected. 0 -no alarm 1 - alarm detected t able 200: c hannel l ine i nterface c ontrol r egister 4 (clicr4 0 x n005 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved dmod flsd lcv_ofd reserved aisd rlosd qrpd ro ro ro ro ro ro ro ro 0 0 0 0 0 0 0 0
preliminary XRT86SH221 224 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - reserved bit 6 - digital monitor output interrupt status 0 - disabled 1 - change of status occurred bit 5 - fifo limit status interrupt status 0 - disabled 1 - change of status occurred bit 4 - line code violation / over flow interrupt s tatus 0 - disabled 1 - change of status occurred bit 3 - reserved bit 2 - alarm indication signal interrupt status 0 - disabled 1 - change of status occurred bit 1 - receive loss of signal interrupt status 0 - disabled 1 - change of status occurred bit 0 - prbs / qrss random pattern interrupt status 0 - disabled 1 - change of status occurred t able 201: c hannel l ine i nterface c ontrol r egister 3 (clicr3 0 x n006 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved dmois flsis lcv_ofis reserved aisis rlosis qrpis rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 225 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - line code violation counter enable this bit enables a 16-bit lcv counter for this part icular channel. 0 - disabled 1 - enabled bit [6:5] - reserved bit 4 - reset all lcv counters although each channel has independent control over its lcv counter, this bit grants access to reset al l 21 lcv counters with one write. this bit must be set to 1 for at le ast 1ms. 0 - normal operation 1 - reset all 21 lcv counters bit 3 - update all lcv counters although each channel has indepedent control over i ts lcv counter, this bit grants access to update al l 21 lcv counters with one write dependent on the bytesel bi t in this register. once initiated, if the bytesel bit is set to 0, the low byte of all 21 lcv counter values will be u pdated to register clicr17 for each channel. conver sely, if the bytesel bit is set to 1, the high byte of all 21 lc v counter values will be updated to register clcr16 for each channel. 0 - normal operation 1 - update all 21 lcv counters bit 2 - lcv counter byte select this bit is used select which between the lower and upper bytes while updating the holding registers. 0 - lower byte is selected 1 - upper byte is selected bit 1 - update channel lcv counter this bit update this channels lcv counter dependen t on the bytesel bit in this register. once initiat ed, if the bytesel bit is set to 0, the low byte of the lcv co unter values will be updated to register clicr17. c onversely, if the bytesel bit is set to 1, the high byte of the l cv counter values will be updated to register clcr1 6. 0 - normal operation 1 - update this channels lcv counter bit 0 - reset channel lcv counters although each channel has independent control over its lcv counter, this bit grants access to reset al l 21 lcv counters with one write. this bit must be set to 1 for at le ast 1ms. 0 - normal operation 1 - reset this channels lcv counter t able 202: c hannel l ine i nterface c ontrol r egister 2 (clicr2 0 x n007 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lcntr_enb reserved rstall updateall bytesel update rst r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 226 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - high byte of the line code violation co unter [15:8] these bits reflect the msb of the current value in the lcv counter once its updated in register clicr 7. bit [7:0] - low byte of the line code violation cou nter [7:0] these bits reflect the lsb of the current value in the lcv counter once its updated in register clicr 7. t able 203: c hannel l ine i nterface c ontrol r egister 1 (clicr1 0 x n010 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hibyte[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 204: c hannel l ine i nterface c ontrol r egister 0 (clicr0 0 x n011 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lobyte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 227 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5
preliminary XRT86SH221 228 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 6.10 e1 synchronization framer register descriptions (egress direction only) bit [7:2] - reserved bit [1:0] - clock source select the css bits are used to select the source of the e gress transmit clock for the line interface. 00 - the recovered received channel input clock is chosen as the transmit clock 01 - the de-mapped channel input clock is chosen as the transmit clock. 10 - the internal master clock derived from the pll is chosen as the transmit clock 11 - same as setting 00 t able 205: c lock s elect r egister (csr 0 x n100 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved css[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 229 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:2] - reserved bit [1:0] - slip buffer enable bits this bit is used to enable slip buffer. 00, 11 = buffer is bypassed. 01 = elastic store (slip buffer) is enabled. 10 = buffer acts as a fifo. the data latency is di ctated by fifo latency register. bit [7:5] - reserved bit [4:0] - programmable fifo latency delay these bits fix the distance of slip buffer read and write pointers in fifo mode. t able 206: s lip b uffer c ontrol r egister (sbcr 0 x n116 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved sb_enb[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 207: fifo l atency r egister (fifolr 0 x n117 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved latency[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 1 0 0
preliminary XRT86SH221 230 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - force re-sync process, auto clear after syn chronization this bit forces frame to restart synchronization pr ocess. this bit is cleared automatically after syn chronization has been reached. 0 - no re-sync 1 - force re-sync bit [6:5] - cas re-synchronization criteria these bits determine the criteria of loss of cas mu ltiframe alignment. 00 - two consecutive multiframe alignment signal (m as) errors. 01 - three consecutive multiframe alignment signal (mas) errors. 10 - four consecutive multiframe alignment signal ( mas) errors. 11 - eight consecutive multiframe alignment signal (mas) errors10 - cas multiframe alignment algorithm 2 (g.732) is enabled. bit [4:3] - crc re-synchronization criteria these bits determine the criteria of loss of crc-4 multiframe alignment. 00 - declare loss of crc multiframe alignment if fo ur consecutive crc multiframe alignment signals hav e been received in error. 01 - declare loss of crc multiframe alignment if tw o consecutive crc multiframe alignment signals have been received in error. 10 - declare loss of crc multiframe alignment if ei ght consecutive crc multiframe alignment signals ha ve been received in error. 11 - declare loss of crc multiframe alignment if 91 5 or more crc-4 errors have been detecteded in one second. bit [2:0] - fas re-synchronization criteria these bits represent the number of consecutive erro red fas patterns to cause the declaration of loss of fas alignment. zero is illegal. the default is set to 011b. t able 208: f raming s elect r egister r e -s ync (fsrrs 0 x n10b h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rsync casc[1:0] crcc[1:0] fasc[2:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 1 0 0 0 0 1 1
XRT86SH221 preliminary 231 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:3] - reserved bit 2 - slip buffer interrupt bit 1 - reserved bit 0 - e1 framer interrupt bit [7:3] - reserved bit 2 - slip buffer interrupt enable bit 1 - reserved bit 0 - e1 framer interrupt enable t able 209: b lock i nterrupt s tatus r egister (bisr 0 x nb00 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved slip reserved e1frame r r r r r r r r 0 0 0 0 0 0 0 0 t able 210: b lock i nterrupt e nable r egister (bier 0 x nb01 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved slip_enb reserved e1frm_enb r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 232 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - lof alarm state this bit is used to indicate that a loss of frame a lignment has occurred. 0 - no red alarm occurs. 1 - red alarm occurs. bit [6:3] - reserved bit 2 - lof state change this bits indicates the change of lof defect (defde t=1) or red alarm (defdet=0) state. 0 - no state change of red alarm is recorded. 1 - the state of red alarm has changed. bit [1:0] - reserved bit [7:3] - reserved bit 2 - red alarm state change interrupt enable setting this bit will enable the interrupt generati on when the change state of red alarm has been dete cted. 0 = disables the interrupt generation of loss of fr ame detection. 1 = enables the interrupt generation of loss of fra me detection. bit [1:0] - reserved t able 211: a larm and e rror s tatus r egister (aesr 0 x nb02 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rxlof_state reserved rxlof reserved ro ro ro ro ro rur/wc rur/wc rur/wc 0 0 0 0 0 0 0 0 t able 212: a larm and e rror i nterrupt e nable r egister (aeier 0 x nb03 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved rxred_enb reserved r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 233 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - change of cas multiframe alignment this bit is used to indicate that the receive synch ronization signal has changed cas multiframe alignm ent with respect to its last multiframe position. 0 - no comfa occurs. 1 - comfa occurs. bits [6:5] - reserved bit 4 - change of frame alignment this bit is used to indicate that the receive synch ronization signal has changed alignment with respec t to its last multiframe position. 0 - no cofa occurs. 1 - cofa occurs. bit 3 - in-frame state this bit indicates the occurrence of state change o f in-frame indication. 0 - no state change occurs of in-frame indication. 1 - in-frame indication has changed state. bit 2 - frame mimic state change this bit indicates the occurrence of state change o f framing mimic detection. 0 - no state change occurs of framing mimic detecti on. 1 - framing mimic detection has changed state. bit 1 - synchronization bit error this bit indicates the occurrence of synchronizatio n bit error event. 0 - no synchronization bit error occurs. 1 - synchronization bit error occurs. bit 0 - framing error ? this bit is used to indicate that one or more frame alignment bit error have occurred. this bit doesn' t not necessarily indicate that synchronization has been lost. 0 - no framing bit error occurs. 1 - framing bit error occurs. t able 213: f ramer i nterrupt s tatus r egister (fisr 0 x nb04 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 comfa reserved cofa if fmd se fe rur/wc rur/wc rur/wc rur/wc rur/wc rur/wc rur/wc rur/wc 0 0 0 0 0 0 0 0
preliminary XRT86SH221 234 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - change of cas frame alignment interrupt ena ble setting this bit will enable the interrupt generati on when the frame search logic determines that cas multiframe alignment has been reached and that the new alignme nt differs from the previous alignment. 0 - disables the interrupt generation of comfa dete ction. 1 - enables the interrupt generation of comfa detec tion. bits [6:5] - reserved bit 4 - change of frame alignment interrupt enable setting this bit will enable the interrupt generati on when the frame search logic determines that fram e alignment has been reached and that the new alignment differs fro m the previous alignment. 0 - disables the interrupt generation of cofa detec tion. 1 - enables the interrupt generation of cofa detect ion. bit 3 - in-frame interrupt enable setting this bit will enable the interrupt generati on of an in-frame recognition. 0 - disables the interrupt generation of an in-fram e detection. 1 - enables the interrupt generation of an in-frame detection. bit 2 - frame mimic detection interrupt enable setting this bit will enable the interrupt generati on when the frame search logic detects the presence of framing bit mimics. 0 - disables the interrupt generation of framing mi mic detection. 1 - enables the interrupt generation of framing mim ic detection. bit 1 - synchronization bit error interrupt enable se_enb : setting this bit will enable the generatio n of an interrupt when a synchronization bit error event has been detected. a synchronization bit error event is def ined as crc-4 error. 0 - the detection of synchronization bit errors doe s not generate an interrupt. 1 - the detection of synchronization bit errors doe s generate an interrupt bit 0 - framing error interrupt enable this bits enables the generation of an interrupt wh en a framing bit error has been detected. 0 - any error in the framing bits does not generate an interrupt. 1 - a error in the framing bits does generate an in terrupt. t able 214: f ramer i nterrupt e nable r egister (fier 0 x nb05 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 comfa_enb reserved cofa_enb if_enb fmd_enb se_enb fe_enb r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 235 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:3] - reserved bit 2 - slip buffer fills & a frame is deleted this bit is set when the elastic store fills and a frame is deleted. bit 1 - slip buffer empties and a frame is repeated this bit is set when the elastic store empties and a frame is repeated. bit 0 - receive slips this bit is set when the slip buffer slips. bit [7:3] - reserved bit 2 - interrupt enable bit for slip buffer full setting this bit enables interrupt when the elastic store fills and a frame is deleted. bit 1 - interrupt enable bit for slip buffer empty setting this bit enables interrupt when the elastic store empties and a frame is repeated. bit 0 - interrupt enable bit for slip buffer slip setting this bit enables interrupt when the slip bu ffer slips. t able 215: s lip b uffer s tatus r egister (sbsr 0 x nb08 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved sb_full sb_empty sb_slip rur/wc rur/wc rur/wc rur/wc rur/wc rur/wc rur/wc rur/wc 0 0 0 0 0 0 0 0 t able 216: s lip b uffer i nterrupt e nable r egister (sbier 0 x nb09 h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved sb_full sb_empty sb_slip r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 236 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 6.11 vt mapping operation control register descripti ons bit [7:4] - reserved bit 3 - latch count a "0 to 1" transition within this bit-field command s each of the vt-de-mapper blocks to update the con tents within the following bit-fields/pmon registers. bit 2 - rei-v enable this read/write bit-field is used to configure a gi ven transmit vt-mapper block to automatically inser t the appropriate rei-v value (based upon the number of b ip-8 bit errors that are detected by the correspond ing receive vt-mapper block) into the v5 byte, within its outbo und vc-12 data-stream. 0 - configures the transmit vt-mapper block to not automatically insert the rei-v value into each v5 b yte, within the outbound vc-12 data-stream. 1 - configures the transmit vt-mapper block to auto matically insert the rei-v value into each v5 byte, within the outbound vc-12 data-stream. t able 217: g lobal vt-m apper b lock - vt m apper b lock c ontrol r egister (vtmcr = 0 x 0c03) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved latch count rei-v enable vt-mapper local loopback [1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it f ields r egister n ame a ddress l ocation vt-payload pointer increment count[3:0] channel cont rol vt mapper block - egress direction - bip-2 error count register - byte 1" 0xnd4a bip-2 error count[11:8] channel control vt mapper bl ock - egress direction - bip-2 error count register - byte 1" 0xnd4a bip-2 error count[7:0] channel control vt mapper blo ck - egress direction - bip-2 error count register - byte 0 0xnd4b vt-payload pointer decrement count[3:0] channel cont rol - vt mapper block - egress direction - rei-v event count register - byte 1 0xnd4e rei-v event count[11:8] channel control - vt mapper block - egress direction - rei-v event count register - byte 1 0xnd4e rei-v event count[7:0] channel control - vt mapper b lock - egress direction - rei-v event count register - byte 0 0xnd4f
XRT86SH221 preliminary 237 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [1:0] - vt mapper local loopback: this read/write bit-field permits the user to confi gure the XRT86SH221 device to operate in the "vt ma pper local loopback" mode. if the user configures the xrt86sh 221 device to operate in this mode, then the output from the vt- mapper block will be internally looped back into th e input of the vt-de-mapper block. bit 7 - latch error count a 0 to 1 transition within this bit-field commands the test pattern receiver to latch its current bit error count into bits 6 - 0 (test pattern error count[14:8]) and bit [7:0] (test pattern error count[7:0]) within the vt mappe r - test pattern detector error count register (address locations = 0x0c16 and 0x0c17). bit 6 - insert pattern error this bit-field is used to configure the vt-mapper t est pattern generator block to insert a single bit- error into the outbound vt data-stream. a 0 to 1 transition withi n this bit-field will command the vt-mapper test pa ttern generator block to insert a single bit-error into the outboun d vt data-stream. bits [5:0] - reserved vt m apper l ocal l oopback [1:0] vt m apper l ocal l oopback t ype 00 no loopback 01 local timing vt mapper local loopback mode: the vt mapper block output data stream along with t he external source signals txclk, txbyte_en, and txsos are internally looped-back into the input of the vt demapper block. 10 undefined 11 looptiming vt mapper local loopback mode: the vt mapper block output data stream along with t he internally gener- ated signals lbclk, lbbyte_en, and lbsos are intern ally looped-back into the input of the vt demapper block. t able 218: g lobal vt m apper b lock - t est p attern c ontrol r egister 1 (vtmtpcr1 = 0 x 0c0e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 latch error count insert pat- tern error reserved r/w r/w r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 238 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - reserved bit [5:4] - vt2 transmit test pattern[1:0] this read/write bit-field is used to specify the te st pattern that the vt2 test pattern generator will generate and transmit. bit [3:0] - reserved t able 219: g lobal vt-m apper b lock - t est p attern c ontrol r egister 0 (vtmtpcr0 = 0 x 0c0f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved vc-12 transmit test pat- tern[1:0] reserved r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 transmitted test pattern vc-12 t ransmit t est p attern [1:0] t est p attern t ransmitted 00 all zeros pattern 01 all ones pattern 10 repeating 1010 pattern 11 2^15-1 prbs pattern
XRT86SH221 preliminary 239 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:6] - test channel size[1:0]: these two read/write bit-fields are used to specify the size of the test channel (e.g., the channel th at will be used to transport the user-specified test pattern. bit 5 - test channel drop side sdh this read/write bit-field is used to select the sou rce of the test channel. in this case, the user ca n either select either a e1 channel originating from the receive sd h block or a e1 channel originating from the ingres s direction e1 blocks. 0 - configures the test channel source to be one of the e1 channels, originating from the ingress dire ction e1 blocks. 1 - configures the test channel source to be the e1 channels, originating from the receive sdh blocks bit [4:0] - test channel drop side[4:0] these read/write bit-fields are used to select whic h data-stream will be output via the test channel. t able 220: g lobal vt-d e m apper b lock - t est p attern d rop r egister 1 (vtdtpdr1 = 0 x 0c12) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test channel size[1:0] test channel drop side sdh test channel drop side[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 test channel size t est c hannel s ize [1:0] t est c hannel s ize 00 reserved 01 reserved 10 vc-12 11 reserved output data stream via test channel t est c hannel d rop s ide [4:0] t est c hannel u sed 00000 unequipped 00001 e1 channel 1 00010 e1 channel 2 00011 e1 channel 3 00100 reserved 00101 e1 channel 4 00110 e1 channel 5 00111 e1 channel 6 01000 reserved 01001 e1 channel 7 01010 e1 channel 8
preliminary XRT86SH221 240 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 01011 e1 channel 9 01100 reserved 01101 e1 channel 10 01110 e1 channel 11 01111 e1 channel 12 10000 reserved 10001 e1 channel 13 10010 e1 channel 14 10011 e1 channel 15 10100 reserved 10101 e1 channel 16 10110 e1 channel 17 10111 e1 channel 18 11000 reserved 11001 e1 channel 19 11010 e1 channel 20 11011 e1 channel 21 11100 reserved 11101 ais will be generated 11110 test channel input 11111 user selected test pattern output data stream via test channel t est c hannel d rop s ide [4:0] t est c hannel u sed
XRT86SH221 preliminary 241 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:6] - receive (expected) pattern: this read/write bit-field is used to specify the te st pattern, that the vt-mapper pattern receiver sho uld be expecting, as shown in the table below. bit 5 - test channel drop-side sdh this read/write bit-field is used to select which s et of e1 traffic should be used, as a basis of comp arison against the test signal. in this case, the user can either select the either the e1 traffic originating from the ingress direction e1 blocks or the e1 traffic originating from the recei ve sdh blocks. 0 - configures the pattern receiver to compare the test signal with one of the e1 channels, originatin g from the ingress direction e1 blocks. 1 - configures the pattern receiver to compare the test signal with one of the e1 channels, originatin g from the receive sdh blocks. bit [4:0] - test channel drop side[4:0]: these read/write bit-fields are used to select whic h data-stream will be compared with the test signal . t able 221: g lobal vt-d e m apper b lock - t est p attern d rop r egister 0 (vtdtpdr0 = 0 x 0c13) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive (expected) pat- tern[1:0] test channel drop side - sdh test channel drop side[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 expected test pattern r eceive (e xpected ) p attern [1:0] e xpected t est p attern 00 all zeros pattern 01 all ones pattern 10 repeating 1010 pattern 11 2 15 -1 prbs pattern test channel selection t est c hannel d rop s ide [4:0] t est c hannel u sed 00000 unequipped 00001 e1 channel 1 00010 e1 channel 2 00011 e1 channel 3 00100 reserved 00101 e1 channel 4 00110 e1 channel 5 00111 e1 channel 6 01000 reserved
preliminary XRT86SH221 242 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 01001 e1 channel 7 01010 e1 channel 8 01011 e1 channel 9 01100 reserved 01101 e1 channel 10 01110 e1 channel 11 01111 e1 channel 12 10000 reserved 10001 e1 channel 13 10010 e1 channel 14 10011 e1 channel 15 10100 reserved 10101 e1 channel 16 10110 e1 channel 17 10111 e1 channel 18 11000 reserved 11001 e1 channel 19 11010 e1 channel 20 11011 e1 channel 21 11100 reserved 11101 ais will be generated 11110 test channel input 11111 disable pattern receiver test channel selection t est c hannel d rop s ide [4:0] t est c hannel u sed
XRT86SH221 preliminary 243 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - vt-mapper test pattern sync: this read-only bit-field indicates whether or not t he vt-mapper pattern receiver is currently declarin g pattern sync with the incoming test signal. 0 - vt-mapper pattern receiver is not currently dec laring pattern sync with the incoming test signal. 1 - vt-mapper pattern receiver is currently declari ng pattern sync with the incoming test signal. bit [6:0] - test pattern error count[14:8]: these seven (7) reset-upon-read bit-fields, along w ith the test pattern error count[7:0] bit-fields fu nction as a 15- bit pattern bit error count register. if the vt-ma pper pattern receiver is currently declaring patter n sync with the designated test signal, then it will increment this register (by the value of 1) each time that it det ects pattern bit error. these seven (7) bit-fields function as the seven mo st-significant bits of this 15-bit counter. bit [7:0] - test pattern error count[7:0]: these eight (8) reset-upon-read bit-fields, along w ith the test pattern error count[14:8] bit-fields f unction as a 15- bit pattern bit error count register. if the vt-ma pper pattern receiver is currently declaring patter n sync with the designated test signal, then it will increment this register (by the value of 1) each time that it det ects pattern bit error. these eight (8) bit-fields function as the eight le ast-significant bits of this 15-bit counter. t able 222: g lobal vt-d e m apper - t est p attern d etector e rror c ount r egister 1 (vtdtpdecr1 = 0 x 0c16) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt-mapper test pattern sync test pattern error count[14:8] r/o rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 223: g lobal vt-d e m apper - t est p attern d etector e rror c ount r egister 0 (vtdtpdecr0 = 0 x 0c17) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test pattern error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 244 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - reserved: bit [5:4] - transmit tributary size select for vt# 6[1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the transmit vt-mapper block (associated with virtual tributary group # 6) will support. n ote : this configuration setting only applies to the tran smit vt-mapper block. this configuration setting d oes not configure the receive vt-de-mapper block to expect any particular vt-type within vt group # 6. the us er must separately configure the receive vt-de-mapper block's handling of vt-group # 6 by setting bits 4 and 5 (rxtributary size select - vt# 6[1:0]) within the v t-mapper - receive tributary size select register ( address = 0x0c1e). bit [3:2] - transmit tributary size select for vt# 5[1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the transmit vt-mapper block (associated with virtual tributary group # 5) will support. t able 224: g lobal vt-m apper - t ransmit t ributary s ize s elect r egister 1 (vtmttssr1 = 0 x 0c1a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved txtributary size select - vt#6[1:0] txtributary size select - vt#5[1:0] txtributary size select - vt#4[1:0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 1 1 1 1 1 1 size of vt #6 t x t ributary s ize s elect - vt#6[1:0] r esulting s ize of vt # 6 00 reerved 01 reserved 10 vc-12 11 reserved size of vt #5 t x t ributary s ize s elect - vt#5[1:0] r esulting s ize of vt # 5 00 reerved 01 reserved 10 vc-12 11 reserved
XRT86SH221 preliminary 245 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [1:0] - transmit tributary size select for vt# 4[1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the transmit vt-mapper block (associated with virtual tributary group # 4), will support. size of vt #4 t x t ributary s ize s elect - vt#4[1:0] r esulting s ize of vt # 4 00 reerved 01 reserved 10 vc-12 11 reserved
preliminary XRT86SH221 246 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - transmit tributary size select for vt# 3[1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the transmit vt-mapper block (associated with virtual tributary group # 3), will support. bit [5:4] - transmit tributary size select for vt# 2[1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the transmit vt-mapper block (associated with virtual tributary group # 2) will support. bit [3:2] - transmit tributary size select for vt# 1[1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the transmit vt-mapper block (associated with virtual tributary group # 1) will support. t able 225: g lobal vt-m apper - t ransmit t ributary s ize s elect r egister 0 (vtmttssr0 = 0 x 0c1b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txtributary size select - vt#3[1:0] txtributary size select - vt#2[1:0] txtributary size select - vt#1[1:0] txtributary size select - vt#0[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 txtributary size select of vt#3 t x t ributary s ize s elect - vt#3[1:0] r esulting s ize of vt # 3 00 reerved 01 reserved 10 vc-12 11 reserved txtributary size select of vt#2 t x t ributary s ize s elect - vt#2[1:0] r esulting s ize of vt # 2 00 reerved 01 reserved 10 vc-12 11 reserved txtributary size select of vt#1 t x t ributary s ize s elect - vt#1[1:0] r esulting s ize of vt # 1 00 reerved 01 reserved 10 vc-12 11 reserved
XRT86SH221 preliminary 247 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [1:0] - transmit tributary size select for vt# 0[1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the transmit vt-mapper block (associated with virtual tributary group # 0) will support. txtributary size select of vt#0 t x t ributary s ize s elect - vt#0[1:0] r esulting s ize of vt # 0 00 reerved 01 reserved 10 vc-12 11 reserved
preliminary XRT86SH221 248 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - reserved: bit [5:4] - receive tributary size select for vt# 6 [1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the receive vt-mapper block (associated with virtual tributary group # 6) will support. bit [3:2] - receive tributary size select for vt# 5 [1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the receive vt-mapper block (associated with virtual tributary group # 5) will support. bit [1:0] - receive tributary size select for vt# 4 [1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the receive vt-mapper block (associated with virtual tributary group # 4) will support. t able 226: g lobal vt-d e m apper - r eceive t ributary s ize s elect r egister 1 (vtdrtssr1 = 0 x 0c1e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved rxtributary size select - vt#6[1:0] rxtributary size select - vt#5[1:0] rxtributary size select - vt#4[1:0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 1 1 1 1 1 1 resulting size of vt#6 r x t ributary s ize s elect - vt#6[1:0] r esulting s ize of vt # 6 00 reerved 01 reserved 10 vc-12 11 reserved resulting size of vt#5 r x t ributary s ize s elect - vt#5[1:0] r esulting s ize of vt # 5 00 reerved 01 reserved 10 vc-12 11 reserved resulting size of vt#4 r x t ributary s ize s elect - vt#4[1:0] r esulting s ize of vt # 4 00 reerved 01 reserved 10 vc-12 11 reserved
XRT86SH221 preliminary 249 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:6] - receive tributary size select for vt# 3 [1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the receive vt-mapper block (associated with virtual tributary group # 3) will support. bit [5:4] - receive tributary size select for vt# 2 [1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the receive vt-mapper block (associated with virtual tributary group # 2) will support. bit [3:2] - receive tributary size select for vt# 1 [1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the receive vt-mapper block (associated with virtual tributary group # 1) will support. t able 227: g lobal vt-d e m apper - r eceive t ributary s ize s elect r egister 0 (vtdrtssr0 = 0 x 0c1f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rxtributary size select - vt#3[1:0] rxtributary size select - vt#2[1:0] rxtributary size select - vt#1[1:0] rxtributary size select - vt#0[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 resulting size of vt#3 r x t ributary s ize s elect - vt#3[1:0] r esulting s ize of vt # 3 00 reerved 01 reserved 10 vc-12 11 reserved resulting size of vt#2 r x t ributary s ize s elect - vt#2[1:0] r esulting s ize of vt # 2 00 reerved 01 reserved 10 vc-12 11 reserved resulting size of vt#1 r x t ributary s ize s elect - vt#1[1:0] r esulting s ize of vt # 1 00 reerved 01 reserved 10 vc-12 11 reserved
preliminary XRT86SH221 250 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [1:0] - receive tributary size select for vt# 0 [1:0]: these two read/write bit-fields are used to specify the vt-size (or the bit-rate to be supported by) t hat the receive vt-mapper block (associated with virtual tributary group # 0) will support. resulting size of vt#0 r x t ributary s ize s elect - vt#0[1:0] r esulting s ize of vt # 0 00 reerved 01 reserved 10 vc-12 11 reserved
XRT86SH221 preliminary 251 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - receive (ingress direction) e1 ais defect d eclared: this read/write bit-field indicates whether or not the corresponding e1 signal (that is being handled by this transmit vt-mapper block) is transporting the ais indicator. 0 - indicates that the ingress direction e1 signal is not currently transporting the ais indicator. 1 - indicates that the ingress direction e1 signal is currently transporting the ais indicator. bit 6 - receive e1 loss of clock defect declared: this read/write bit-field indicates whether the tra nsmit vt-mapper block is currently declaring the lo ss of clock defect condition within the corresponding ingress d irection e1 signal. 0 - indicates that the transmit vt-mapper block is not currently declaring the loss of clock defect co ndition with the corresponding e1 signal. 1 - indicates that the transmit vt-mapper block is currently declaring the loss of clock defect condit ion with the corresponding e1 signal. bit 5 - bip-2 error insert into v5 this read/write bit-field is used to configure the corresponding transmit vt-mapper block to transmit erred bip-2 bits to the remote terminal equipment. if the user invokes this feature, then the transmit vt-mapper block will automatically invert the value of the locally-compu ted bip-2 bits, prior to transmitting this data to the remote terminal equipment. 0 - configures the transmit vt-mapper block to not transmit erred bip-2 bits to the remote terminal eq uipment. 1 - configures the transmit vt-mapper block to tran smit erred bip-2 bits to the remote terminal equipm ent. n ote : for normal operation, the user should set this bit- field to 0. bit [4:2] - vt label[2:0]: these two read/write bit-fields are used to set the vt label bit-fields (within each outbound v5 byte) the value of the users choice. bit 1 - auto transmit rfi-v indicator this read/write bit-field is used to select the sou rce of the rfi-v bit-field, within the v5 byte of e ach outbound vc- 12 traffic. 0 - configures the transmit vt-mapper block to use the on-chip register as the source of the rfi-v bit -field. 1 - configures the transmit vt-mapper block to set the rfi-v bit-fields to the appropriate value, base d upon any defects that the corresponding receive vt-mapper bl ock is currently declaring. t able 228: c hannel c ontrol - vt-m apper e1 i nsertion c ontrol r egister 1 (vtme1icr1 = 0 x nd42) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ingress direction e1 ais defect declared ingress e1 loss of clock defect declared bip-2 error insert vt signal label[2:0] auto transmit rfi-v indicator auto transmit rdi-v indicator r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 252 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 0 - auto transmit rdi-v indicator this read/write bit-field is used to select the sou rce of the rdi-v bit-field, within the v5 byte of e ach outbound vt2 traffic. the transmit vt-mapper block will set the rdi-v bit-fields to the appropriate value, based up on any defect conditions that are currently being declared by the corresponding receive vt-mapper block. 0 - configures the transmit vt-mapper block to use the on-chip register as the source of the rdi-v bit -field. 1 - configures the transmit vt-mapper block to set the rdi-v bit-fields to the appropriate value, base d upon any defects that the corresponding receive vt-mapper bl ock is currently declaring.
XRT86SH221 preliminary 253 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - transmit rfi-v value: this read/write bit-field is used to exercise softw are control over the state of the rfi-v bit-field ( within each v5 byte) of the outbound vt data-stream. if the user sets bit 1 (auto transmit rfi-v indicator), within the vt-mapper block - ingress direction - e1 insertion control re gister - 2 to 0, then the transmit vt-mapper block will read out the contents within this bit-field, and it will load th is value into the rfi-v bit-field within each v5 by te of the outbound vt- data-stream. n ote : this bit-field is ignored if the user sets bit 1 (a uto transmit rfi-v indicator), within the vt mapper block - ingress direction - e1 insertion control register - 1 to 1. bit 6 - transmit rdi-v value: this read/write bit-field is used to exercise softw are control over the state of the rdi-v bit-field ( within each v5 byte) of the outbound vt data-stream. if the user sets bit 0 (auto transmit rdi-v indicator), within the vt-mapper block - ingress direction - e1 insertion control re gister - 2 to 0, then the transmit vt-mapper block will read out the contents within this bit-field, and it will load th is value into the rdi-v bit-field within each v5 by te of the outbound vt- data-stream. n ote : this bit-field is ignored if the user sets bit 0 (a uto transmit rdi-v indicator), within the vt mapper block - ingress direction - e1 insertion control register - 1 to 1. bit 5 - transmit ais-v indicator this read/write bit-field is used to command the tr ansmit vt-mappper block to transmit the ais-v indic ator (within the corresponding vt2) within the outbound vt-data -stream. 0 - configures the transmit vt-mapper block to not transmit the ais-v indicator within the outbound vt -data-stream. 1 - configures the transmit vt-mapper block to tran smit the ais-v indicator within the outbound vt-dat a-stream. bit [4:0] - e1 (cross-connect) channel select[4:0]: these read/write bit-fields is used to configure th e internal vt-cross connect. more specifically, th ese read/ write bit-fields are used to select which (of the 2 1 ingress direction) e1 signals to be mapped into e ither a vt2 by this particular transmit vt-mapper block. the foll owing table presents the relationship between the s ettings of these bit-fields and the resulting cross connect configur ation. t able 229: c hannel c ontrol - vt-m apper e1 i nsertion c ontrol r egister 0 (vtme1icr0 = 0 x nd43) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit rfi-v value transmit rdi-v value transmit ais-v indicator e1 cross connect channel select_ingress direction[4 :0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 cross connect configuration e1 (c ross -c onnect ) c hannel s elect [4:0] r esulting i ngress d irection e1 c hannel being handled by this particular t ransmit vt-m apper block c omments 00000 unequipped this particular vt will be transmitt ed as an un-equipped signal 00001 ingress direction e1 channel 1 00010 ingress direction e1 channel 2 00011 ingress direction e1 channel 3 00100 reserved 00101 ingress direction e1 channel 4 00110 ingress direction e1 channel 5
preliminary XRT86SH221 254 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 00111 ingress direction e1 channel 6 01000 reserved 01001 ingress direction e1 channel 7 01010 ingress direction e1 channel 8 01011 ingress direction e1 channel 9 01100 reserved 01101 ingress direction e1 channel 10 01110 ingress direction e1 channel 11 01111 ingress direction e1 channel 12 10000 reserved 10001 ingress direction e1 channel 13 10010 ingress direction e1 channel 14 10011 ingress direction e1 channel 15 10100 reserved 10101 ingress direction e1 channel 16 10110 ingress direction e1 channel 17 10111 ingress direction e1 channel 18 11000 reserved 11001 ingress direction e1 channel 19 11010 ingress direction e1 channel 20 11011 ingress direction e1 channel 21 11100 reserved 11101 none 11110 the test channel 11111 test pattern - from vt pattern generator cross connect configuration e1 (c ross -c onnect ) c hannel s elect [4:0] r esulting i ngress d irection e1 c hannel being handled by this particular t ransmit vt-m apper block c omments
XRT86SH221 preliminary 255 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:4] - rdi-v accepted value[3:0]: these read-only bit-fields reflect the most recentl y value for rdi-v that has been accepted (or valida ted) by the receive vt-mapper block. the receive vt-mapper blo ck will accept (or validate) a given rdi-v value, o nce it has received this same rdi-v value, within rdi-v_accept _threshold[3:0] number of consecutive, incoming vt multi- frames. n otes : 1. these bit-fields are only active if the user has configured the receive vt-de-mapper block to suppor t erdi-v (enhanced rdi-v). 2. these bit-fields reflect the four-bit rdi-v value that the vt de-mapper block has accepted via the k 4 bytes within the incoming vt/tu data-stream. bit [3:0] - rdi-v accept threshold[3:0]: these read/write bit-fields are used to define the rdi-v validation criteria for the receive vt-mapper block. more specifically, these bit-fields are used to specify the number of consecutive, incoming vt multi-frame, in which the receive vt-mapper block must receive a given rdi-v value before it validates it and loads it into bit[ 7:4] (rdi-v accepted value[3:0]). bit 7 - reserved: bit [6:1] - unused: bit 0 - rdi-v type: this read/write bit-field is used to configure the vt-de-mapper blocks (associated with a given channe l) to support either the srdi-v (single bit - rdi-v) or erdi-v (e xtended - rdi-v) form of signaling. if the user us es only single-bit rdi-v, then the rdi-v indicator will only be transp orted via bit 0 (rdi-v) within the v5 byte in a vt- data-stream. conversely, if a user uses extended rdi-v, then the rdi-v indicator will be transported via both bits 0 (rdi-v) within the v5 byte, and bits 3, 2 and 1 within the z7/k4 b yte. 0 - configures the vt-de-mapper blocks to use the s rdi-v form of signaling. 1 - configures the vt-de-mapper blocks to use the e rdi-v form of signaling. n ote : this configuration setting only applies to the vt-d e-mapper block. if the user wishes to configure th e vt- mapper block to support either the "srdi-v" or the "erdi-v" form of signaling, then he/she must set bi t 1 (rdi- v type) within the "channel control - vt-mapper blo ck - ingress direction - transmit rdi-v control reg ister - byte 0" to the appropriate state. t able 230: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 3 (vtde1dcr3 = 0 x nd44) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdi-v accepted value[3:0] rdi-v accept threshold[3:0 ] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 231: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 2 (vtde1dcr2 = 0 x nd45) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved rdi-v type r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 256 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - vt error event declared: this read-only bit-field indicates that at least on e of the following defects, errors or note-worthy c onditions are currently being declared. ? vt size error ? lop-v defect declared ? change in vt label event ? ais-v defect declared ? ais-v failure declared ? rfi-v defect declared ? rdi-v defect declared 0 - indicates that none of these above-mentioned de fects, errors or note-worthy conditions are current ly being declared. 1 - indicates that at least one of the above-mentio ned events are currently being declared. bit 6 - vt size errodefect declared: this read-only bit-field indicates whether or not t he receive vt-de-mapper block is currently declarin g the vt size error defect condition. the receive vt-de-mapper b lock will declare the vt size error defect conditio n anytime it receives a vt data-stream with v1 bytes that contai ns the incorrect vt-size bit values, as depicted be low. 0 - indicates that the receive vt-de-mapper block i s not currently declaring the vt size error defect condition. 1 - indicates that the receive vt-de-mapper block i s currently declaring the vt size error defect cond ition. bit 5 - lop-v defect declared: this read-only bit-field indicates whether or not t he receive vt-mapper block is currently declaring t he lop-v defect condition. 0 - indicates that the receive vt-de-mapper block i s currently not declaring the lop-v defect conditio n. 1 - indicates that the receive vt-de-mapper block i s currently declaring the lop-v defect condition bit 4 - change in vt label[2:0] indicator: this read/write 1 to clear bit-field indicates whet her or not the receive vt-de-mapper block has detec ted a change in vt signal label, since the last time the user read and cleared this register bit 0 - indicates that the receive vt-de-mapper block h as not detected a change in vt signal label since t he last time the user read and cleared this register bit. bit [3:1] - vt label value[2:0]: this read-only bit-field reflects the value of the most recently accepted (or validated) vt signal lab el value. bit 0 - ais-v defect declared: this read-only bit-field indicates whether or not t he receive vt-de- mapper block is currently declari ng the ais-v defect condition, or not. 0 - indicates that the receive vt-de-mapper block i s not currently declaring the ais-v defect conditio n. 1 - indicates that the receive vt-de-mapper block i s currently declaring the ais-v defect condition. t able 232: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 1 (vtde1dcr1 = 0 x nd46) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt error event declared vt size error defect declared lop-v defect declared change in vt label value[2:0] indicator vt label value[2:0] ais-v defect declared r/o r/o r/o r/w1c r/o r/o r/o r/o 0 0 1 0 0 0 0 0
XRT86SH221 preliminary 257 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - rfi-v defect declared: this read/write bit-field indicates whether or not the receive vt-de-mapper block is currently declari ng the rfi-v defect condition. 0 - indicates that the receive vt-de-mapper block i s not currently declaring the rfi-v defect conditio n. 1 - indicates that the receive vt-de-mapper block i s currently declaring the rfi-v defect condition. bit 6 - rdi-v defect declared: this read/write bit-field indicates whether or not the receive vt-de-mapper block is currently declari ng the rdi-v defect condition. 0 - indicates that the receive vt-de-mapper block i s not currently declaring the rdi-v defect conditio n. 1 - indicates that the receive vt-de-mapper block i s currently declaring the rdi-v defect condition. bit 5 - force e1 ais in egress direction this read/write bit-field is used to configure this particular receive vt-de-mapper block to transmit the e1 ais indicator within the egress direction of this parti cular e1 channel. 0 - configures the receive vt-de-mapper block to no t transmit the e1 ais pattern within the egress dir ection corresponding to this particular channel. 1 - configures the receive vt-de-mapper block to tr ansmit the e1 ais pattern within the egress directi on corresponding to this particular channel. bit [4:0] - e1 cross connect channel select_egress direction[4:0]: these read/write bit-fields are used to configure t he internal vt-cross connect. more specifically, these read/write bit-fields are used to select which (of the 21 egress direction) e 1 ports, that this particular receive vt-mapper block will route (or d irect) its egress direction e1 signal to. the following table presents the relationship betwe en the settings of these bit-fields and the resulti ng cross-connect configuration. t able 233: c hannel c ontrol - vt-d e m apper e1 d rop c ontrol r egister 0 (vtde1dcr0 = 0 x nd47) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rfi-v defect declared rdi-v defect declared force e1 ais in egress direction e1 cross connect channel select_egress direction[4: 0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 cross connect configuration e1 (c ross c onnect ) c hannel s elect [4:0] r esulting p ort that this r eceive vt-m apper block will direct its e1 t raffic to c omments 00000 unequipped 00001 egress direction e1 signal is routed to the eg ress direction output of e1 channel 1 00010 egress direction e1 signal is routed to the eg ress direction output of e1 channel 2 00011 egress direction e1 signal is routed to the eg ress direction output of e1 channel 3 00100 reserved
preliminary XRT86SH221 258 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 00101 egress direction e1 signal is routed to the eg ress direction output of e1 channel 4 00110 egress direction e1 signal is routed to the eg ress direction output of e1 channel 5 00111 egress direction e1 signal is routed to the eg ress direction output of e1 channel 6 01000 reserved 01001 egress direction e1 signal is routed to the eg ress direction output of e1 channel 7 01010 egress direction e1 signal is routed to the eg ress direction output of e1 channel 8 01011 egress direction e1 signal is routed to the eg ress direction output of e1 channel 9 01100 reserved 01101 egress direction e1 signal is routed to the eg ress direction output of e1 channel 10 01110 egress direction e1 signal is routed to the eg ress direction output of e1 channel 11 01111 egress direction e1 signal is routed to the eg ress direction output of e1 channel 12 10000 reserved 10001 egress direction e1 signal is routed to the eg ress direction output of e1 channel 13 10010 egress direction e1 signal is routed to the eg ress direction output of e1 channel 14 10011 egress direction e1 signal is routed to the eg ress direction output of e1 channel 15 10100 reserved 10101 egress direction e1 signal is routed to the eg ress direction output of e1 channel 16 10110 egress direction e1 signal is routed to the eg ress direction output of e1 channel 17 10111 egress direction e1 signal is routed to the eg ress direction output of e1 channel 18 11000 reserved 11001 egress direction e1 signal is routed to the eg ress direction output of e1 channel 19 11010 egress direction e1 signal is routed to the eg ress direction output of e1 channel 20 cross connect configuration e1 (c ross c onnect ) c hannel s elect [4:0] r esulting p ort that this r eceive vt-m apper block will direct its e1 t raffic to c omments
XRT86SH221 preliminary 259 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 11011 egress direction e1 signal is routed to the eg ress direction output of e1 channel 21 11100 reserved 11101 reserved 11110 reserved 11111 reserved cross connect configuration e1 (c ross c onnect ) c hannel s elect [4:0] r esulting p ort that this r eceive vt-m apper block will direct its e1 t raffic to c omments
preliminary XRT86SH221 260 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:4] - vt payload pointer increment count[3:0] : these reset-upon-read bit-fields reflect the number of vt payload pointer increment events that the re ceive vt- mapper block has detected since the last read of th is register. the receive vt-mapper block will inc rement the contents within these bit-fields each time that it detects a vt payload pointer increment event within the incoming vt data-stream. bit [3:0] - bip-2 error count[11:8]: these reset-upon-read bit-fields, along with those within the vt mapper block - egress direction - bip -2 error count register - byte 0, presents a 12-bit expressi on that reflects the number of bip-2 errors that th e receive vt- mapper block has detected (within the incoming vt-d ata-stream) since the last read of this register. these particular bit-fields are the four most signi ficant bit-fields within this 12-bit expression. bit [7:0] - bip-2 error count[7:0]: these reset-upon-read bit-fields, along with those within the vt mapper block - egress direction - bip -2 error count register - byte 1, presents a 12-bit expressi on that reflects the number of bip-2 errors that th e receive vt- mapper block has detected (within the incoming vt-d ata-stream) since the last read of this register. these particular bit-fields are the eight least sig nificant bit-fields within this 12-bit expression. t able 234: c hannel c ontrol - vt-d e m apper bip-2 e rror c ount r egister 1 (vtdbip2ecr1 = 0 x nd4a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt payload pointer increment count[3:0] bip-2 error count[11:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 235: c hannel c ontrol - vt-d e m apper bip-2 e rror c ount r egister 0 (vtdbip2ecr0 = 0 x nd4b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bip-2 error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 261 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:4] - vt payload pointer decrement count[3:0] : these reset-upon-read bit-fields reflect the number of vt payload pointer decrement events that the re ceive vt- mapper block has detected since the last read of th is register. the receive vt-mapper block will inc rement the contents within these bit-fields each time that it detects a vt payload pointer decrement event within the incoming vt data-stream. bit [3:0] - rei-v event count[11:8]: these reset-upon-read bit-fields, along with those within the vt mapper block - egress direction - rei -v event count register - byte 0, presents a 12-bit expressi on that reflects the number of rei-v events that th e receive vt- mapper block has detected (within the incoming vt-d ata-stream) since the last read of this register. these particular bit-fields are the four most signi ficant bit-fields within this 12-bit expression. bit [7:0] - rei-v event count[7:0]: these reset-upon-read bit-fields, along with those within the vt mapper block - egress direction - rei -v event count register - byte 1, presents a 12-bit expressi on that reflects the number of rei-v events that th e receive vt- mapper block has detected (within the incoming vt-d ata-stream) since the last read of this register. these particular bit-fields are the eight least sig nificant bit-fields within this 12-bit expression. t able 236: c hannel c ontrol - vt-d e m apper rei-v e vent c ount r egister 1 (vtdreiecr1 = 0 x nd4e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt-payload pointer decrement count[3:0] rei-v event count[11:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 237: c hannel c ontrol - vt-d e m apper rei-v e vent c ount r egister 0 (vtdreiecr0 = 0 x nd4f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-v event count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 262 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - event mask - vt channel: this read/write bit-field is used to either enable or disable the channel control - vt error event dec lared bit-field (within the vt-mapper block - ingress direction - e 1 drop control register). if the user disables the vt error event declared re gister bit, then that particular bit-field will nev er be asserted in response to any of the following defects, errors or note-worthy conditions. ? vt size error ? lop-v defect declared ? change in vt label event ? ais-v defect declared ? ais-v failure declared ? rfi-v defect declared ? rdi-v defect declared ? receive elastic store overflow event ? change of receive aps value event 0 - disables the vt error event declared bit-field, entirely 1 - enables the vt error event declared bit-field. bit 6 - vt size error - event mask this read/write bit-field is used to either enable or disable the vt size error defect to/from causing both the vt error event declared and the vt size error event - compos ite bit-fields to be asserted. if the user enables this feature, then the receive vt-de-mapper block will assert bit 7 (v t error event declared) within the channel control - vt mapper block - egress direction - e1 drop control register - byte 1 to 1 anytime it declares the vt size erro r defect condition. conversely, if the user disables this feature, then the receive vt de-mapper block will not assert the vt error event declared bit-field whenever it declares the vt size error defect condition. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the vt size error defect condition. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the vt size error defect condition. bit 5 - lop-v defect - event mask this read/write bit-field permits the user to eithe r enable or disable the lop-v defect defect to/from causing the vt error event declared bit-field to be asserted. if the user enables this feature, then the receive vt de-mapper block will assert bit 7 (vt error event declared) within the channel control - vt mapper block - egress dire ction - e1 drop control register - byte 1 to 1 anytime it declares the lop-v defect condition. conversely, if the use r disables this feature, then the receive vt-de-mapper block will n ot assert the vt error event declared bit-field whe never it declares the lop-v defect condition. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the lop-v defect condition. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the lop-v defect condition t able 238: c hannel c ontrol - vt-d e m apper r eceive aps r egister 1 (vtdrapsr1 = 0 x nd52) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 event mask - vt channel vt size error - event mask lop-v defect - event mask change of vt label - event mask receive elastic store overflow event ais-v fail- ure - event mask ais-v fail- ure declared ais-v defect - event mask r/w r/w r/w r/w r/w1c r/w r/o r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 263 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 4 - change of vt label - event mask this read/write bit-field permits the user to eithe r enable or disable the change of vt label conditio n to/from causing the vt error event declared bit-field to be asserted. if the user enables this feature, then the receive vt-de- mapper block will assert bit 7 (vt error event decl ared) within the channel control - vt mapper block - egress direction - e1 drop control register - byte 1 to 1 anytime it declares the change of vt label conditio n. conversely, if the user disables this feature, then the receive vt -de-mapper block will not assert the vt error event declared bit- field whenever it declares the change of vt label c ondition. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the change of vt label condition. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the change of vt label condition. bit 3 - receive elastic store overflow event this read/w1c bit-field indicates whether or not th e receive elastic store overflow event has occurred (within this tributary) since the last time that the user has wr itten a 1 to clear this bit-field. 0 - indicates that the receive elastic store overfl ow event has not occurred since the last time the u ser has written a 1 to clear this bit-field. 1 - indicates that the receive elastic store overfl ow event has occurred since the last time the user has written a 1 to clear this bit-field. bit 2 - ais-v failure - event mask this read/write bit-field permits the user to eithe r enable or disable the ais-v failure condition to/ from causing the vt error event declared bit-field to be asserted. if the user enables this feature, then the receive vt-de-mapper block will assert bit 7 (vt error event declared) within the channel control - vt mapper block - egress dire ction - e1 drop control register - byte 1 to 1 anytime it declares the ais-v failure condition. conversely, if the us er disables this feature, then the receive vt-de-mapper block will n ot assert the vt error event declared bit-field whe never it declares the ais-v failure condition. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the ais-v failure condition. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the ais-v failure condition. bit 1 - ais-v failure declared this read-only bit-field indicates whether or not t he receive vt-de-mapper block is currently declarin g the ais-v failure condition. the receive vt-de-mapper block will declare the ais -v failure condition if it continuously declares th e ais-v defect condition for 2.5 0.5 seconds. the receive vt de -mapper block will clear the ais-v failure conditio n, whenever it has cleared the ais-v defect condition for 10 0.5 seconds. 0 - indicates that the receive vt-de-mapper block i s not currently declaring the ais-v failure conditi on. 1 - indicates that the receive vt-de-mapper block i s currently declaring the ais-v failure condition. bit 0 - ais-v defect - event mask this read/write bit-field permits the user to eithe r enable or disable the ais-v defect condition to/f rom causing the vt error event declared bit-field to be asserted. if the user enables this feature, then the receive vt-de-mapper block will assert bit 7 (vt error event declared) within the channel control - vt mapper block - egress dire ction - e1 drop control register - byte 1 to 1 anytime it declares the ais-v defect condition. conversely, if the use r disables this feature, then the receive vt-de-mapper block will n ot assert the vt error event declared bit-field whe never it declares the ais-v defect condition. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the ais-v defect condition. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the ais-v defect condition.
preliminary XRT86SH221 264 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - rfi-v defect - event mask: this read/write bit-field permits the user to eithe r enable or disable the rfi-v defect defect to/from causing the vt error event declared bit-field to be asserted. if the user enables this feature, then the receive vt de-mapper block will assert bit 7 (vt error event declared) within the channel control - vt mapper block - egress dire ction - e1 drop control register - byte 1 to 1 anytime it declares the rfi-v defect condition. conversely, if the use r disables this feature, then the receive vt-de-mapper block will n ot assert the vt error event declared bit-field whe never it declares the rfi-v defect condition. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the rfi-v defect condition. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the rfi-v defect condition. bit 6 - rdi-v defect - event mask: this read/write bit-field permits the user to eithe r enable or disable the rdi-v defect defect to/from causing the vt error event declared bit-field to be asserted. if the user enables this feature, then the receive vt de-mapper block will assert bit 7 (vt error event declared) within the channel control - vt mapper block - egress dire ction - e1 drop control register - byte 1 to 1 anytime it declares the rdi-v defect condition. conversely, if the use r disables this feature, then the receive vt-de-mapper block will n ot assert the vt error event declared bit-field whe never it declares the rdi-v defect condition. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the rdi-v defect condition. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the rdi-v defect condition. bit 5 - change of receive aps value - event mask: this read/write bit-field permits the user to eithe r enable or disable the change of aps value event t o/from causing the vt error event declared bit-field to be asserte d. if the user enables this feature, then the rece ive vt-de-mapper block will assert bit 7 (vt error event declared) w ithin the channel control vt mapper block - egress direction - e1 drop control register - byte 1 to 1 anytime it decl ares the change of receive aps value event. conver sely, if the user disables this feature, then the receive vt-de-mappe r block will not assert the vt error event declared bit-field whenever it declares the change of receive aps valu e event. 0 - configures the receive vt-de-mapper block to no t assert the vt error event declared bit-field when ever it declares the change of receive aps value event. 1 - configures the receive vt-de-mapper block to as sert the vt error event declared bit-field whenever it declares the change of receive aps value event. bit 4 - change of receive aps value: this read/w1c bit-field indicates whether or not th e change of receive aps value event has occurred (w ithin this tributary) since the last time that the user has wr itten a 1 to clear this bit-field. the receive vt- de-mapper block will declare the change of receive aps value whenever it has accepted a new value from the k4 bytes within the incoming vt data-stream. 0 - indicates that the change of receive aps value event has not occurred since the last time the user has written a 1 to clear this bit-field. 1 - indicates that the change of receive aps value event has occurred since the last time the user has written a 1 to clear this bit-field. t able 239: c hannel c ontrol - vt-d e m apper r eceive aps r egister 0 (vtdrapsr0 = 0 x nd53) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rfi-v defect event - mask rdi-v defect event - mask change of receive aps value - event mask change of receive aps value receive aps value[3:0] r/w r/w r/w r/w1c r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 265 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [3:0] - receive aps value[3:0]: these four (4) read-only bit-field reflects the aps value that the vt-de-mapper block has received (vi a bits 1 through 4, within the k4 byte) and has validated.
preliminary XRT86SH221 266 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - e1 ais - event mask: this read/write bit-field permits the user to eithe r enable or disable the "change of e1 ais defect co ndition" event to/from causing the "change of e1 ais defect condit ion" interrupt to be generated. if the user enable s this feature, then the vt-mapper block will assert the "change of e1 a is defect condition" interrupt in response to eithe r of the following conditions. ? whenever the vt-mapper block declares the "e1 ais" defect condition within the ingress direction e1 da ta-stream. ? whenever the vt-mapper block clears the "e1 ais" de fect condition within the ingress direction e1 data stream. 0 - configures the vt-mapper block to not generate the "change of e1 ais defect condition" interrupt, whenever it declares or clears the e1 ais defect condition. 1 - configures the vt-mapper block to generate the "change of e1 ais defect condition" interrupt, when ever it declares or clears the "e1 ais defect condition. bit 6 - e1 loss of clock event - event mask: this read/write bit-field permits the user to eithe r enable or disable the "change of e1 loc defect co ndition" event to/from causing the "change of e1 loc defect condit ion" interrupt to be generated. if the user enable s this feature, then the vt-mapper block will assert the "change of e1 loc defect condition" interrupt in response to either of the following conditions. ? whenever the vt-mapper block declares the "e1 loc" defect condition within the ingress direction e1 da ta-stream. ? whenever the vt-mapper block clears the "e1 loc" de fect condition within the ingress direction e1 data stream. 0 - configures the vt-mapper block to not generate the "change of e1 loc defect condition" interrupt, whenever it declares or clears the e1 loc defect condition. 1 - configures the vt-mapper block to generate the "change of e1 loc defect condition" interrupt, when ever it declares or clears the "e1 loc defect condition. bit [5:4] - reserved: bit 3 - transmit elastic store overflow: this read/w1c bit-field indicates whether or not th e vt mapper block has declared a "transmit elastic store overflow" event since the last read of this register. the vt -mapper block will declare a "transmit elastic stor e overflow" event anytime that the "transmit fifo" (within the vt-map per block) has experience an "overflow" event. 0 - indicates that the "transmit elastic store over flow" event has not occurred since the last read of this register. 1 - indicates that the "transmit elastic store over flow" event has occurred since the last read of thi s register. n ote : the vt-mapper block will typically handle "small ti ming offsets" (between the ingress direction e1 sig nal and the "transmit direction" 19.44mhz or 51.84mhz clock signal via bit-stuffing (as it maps this e1 data i nto vts. however, if this bit-field is set to "1", this is t ypically a indication of a significant clock freque ncy accuracy problem within the system. bit [2:0] - reserved: t able 240: c hannel c ontrol - vt-m apper t ransmit aps r egister 1 (vtmtapsr1 = 0 x nd56) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 e1 ais - event mask e1 loc - event mask reserved transmit elastic store overflow reserved r/w r/w r/w r/w w1c r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 267 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - reserved: bit [6:4] - transmit erdi-v[2:0] these three (3) read/write bit-fields permit the us er to exercise software control over the value of t he "erdi-v" bits that are transported via "bits 5 through 7" (within the k4 byte) within the outbound vt data-stream. n ote : this bit-field is only active if both of the follow ing is true. ? the user has configured vt-mapper/de-mapper blocks to support the erdi-v (extended - rdi-v) form of signaling and, ? the user has set bit 6 (transmit rdi-v value) withi n the "channel control - vt mapper block - ingress direction - e1 insertion control register - 0" to " 1". bit [3:0] - transmit aps value[3:0] these four (4) read/write bit-fields permit the use r to exercise software control over the value of th e "aps" bits that are transported via bits 1 through 4 (within the k4 byte) within the outbound vt data-stream. bit [7:0] - tandem connection receive bip-2 error c ount: this reset-upon-read bit-fields present an 8-bit ex pression that reflects the number of bip-2 errors t hat the receive vt-mapper block has detected (within bit-7 and bit- 6 of the n2 byte of the incoming vt-data-stream) si nce the last read of this register. bit [7:0] - tandem connection receive rei-v event c ount: this reset-upon-read bit-fields present an 8-bit ex pression that reflects the number of rei-v events t hat the receive vt-mapper block has detected (within bit-3 of the n2 byte of the incoming vt-data-stream) sinc e the last read of this register. t able 241: c hannel c ontrol - vt-m apper t ransmit aps/k4 r egister 0 (vtmtapsr0 = 0 x nd57) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved txerdi[2:0] txaps[3:0] r/o r/w r/w r/w r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 242: c hannel c ontrol - vt-d e m apper t andem c onnection - r eceive bip-2 e rror c ount r egister 2 (vtdtcbip2ecr = 0 x nd59) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tc_bip_2 error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 243: c hannel c ontrol - vt-d e m apper t andem c onnection - r eceive rei-v e vent c ount r egister 1 (vtdtcreiecr = 0 x nd5b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tc_rei-v event count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 268 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:0] - tandem connection receive oei event cou nt: this reset-upon-read bit-fields present an 8-bit ex pression that reflects the number of oei events tha t the receive vt-mapper block has detected (within bit-2 of the n 2 byte of the incoming vt-data-stream) since the la st read of this register. bit [7:2] - reserved: bit 1 - change of receive aps value event - composi te: this read-only bit-field indicates whether or not t he vt-de-mapper block has detected a change of stat e of the received vt path aps signalling. three consecutive consistent new values for the received vt path aps signal must be detected for this bit to be set. 0 - indicates that the vt-de-mapper block is not cu rrently detecting a change of state of the vt path aps signalling. 1 - indicates that the vt-de-mapper block is curren tly detecting a change of state of the vt path aps signalling. bit 0 - transmit or receive elastic store overflow event - composite: this read-only bit-field indicates whether or not t he vt-de-mapper block has experienced either a rece ive or a transmit elastic store overflow. 0 - indicates that the vt-de-mapper block is not cu rrently declaring a receive or a transmit elastic s tore overflow. 1 - indicates that the vt-de-mapper block is curren tly declaring a receive or a transmit elastic store overflow. t able 244: c hannel c ontrol - vt-d e m apper t andem c onnection - r eceive oei e vent c ount r egister 0 (vtdtcoeiecr = 0 x nd5f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tc_oei event count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 245: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 1 (vtdcsr1 = 0 x nd60) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of receive aps value - composite transmit or receive elastic store over- flow event - composite r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 269 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - vt size error event - composite: this read-only bit-field reports whether or not an incorrect virtual container size bits were received . the valid virtual container size bits are "10" for vt2/tu-12. 0 - indicates that the vt-de-mapper block is not cu rrently receiving an incorrect vt size bits error. 1 - indicates that the vt-de-mapper block is curren tly receiving an incorrect vt size bits error. bit 6 - lop-v defect event - composite: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "v t path loss of pointer" (lop-v) defect condition. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the lop-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the lop-v defect condition. bit 5 - rfi-v defect event - composite: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "r emote failure indicator" (rfi-v) defect condition. three consecu tive vt frames with consistent rfi defect indicator value must be detected for this bit to be set. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the rfi-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the rfi-v defect condition. bit 4 - rdi-v defect event - composite: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "r emote defect indicator" (rdi-v) defect condition. three consecu tive vt frames with consistent rdi defect indicator value must be detected for this bit to be set. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the rdi-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the rdi-v defect condition. bit 3 - ais-v defect event - composite: this read-only bit-field indicates whether or not o ne or more of the vt-de-mapper block is currently d eclaring the "alarm indication signal" (ais-v) defect condition due to one of the vt ais-f fields in the rapsxx reg isters being active and not masked. this bit will be set if ais-v defe ct condition has been declared in any of the 21 vt- de-mapper block. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the ais-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the ais-v defect condition. bit 2 - ais pointer event - composite: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "a larm indication signal pointer" (aisp-v) defect condition. three c onsecutive vt frames with all ones value for v1 and v2 pointer bytes must be detected for this bit to be set. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the aisp-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the aisp-v defect condition. t able 246: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 0 (vtdcsr0 = 0 x nd61) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 vt size error event - composite lop-v defect event - composite rfi-v defect event - composite rdi-v defect event - composite ais-v defect event - composite ais pointer event - composite change in vt label event - composite e1 ais or loc event - composite r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 270 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 1 - change in vt label event - composite: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently detecting a vt l abel change of state event. three consecutive vt frames with a consistently different vt label value must be dete cted for this bit to be set. 0 - indicates that the vt-de-mapper block is not cu rrently detecting a vt label change condition. 1 - indicates that the vt-de-mapper block is curren tly detecting a vt label change condition. bit 0 - e1 ais or loc event - composite: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "a larm indication signal defect" (ais-v) or "loss of clock" (loc-v) d efect condition. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the ais-v or loc-v defect conditi on. 1 - indicates that the vt-de-mapper block is curren tly declaring the ais-v or loc-v defect condition.
XRT86SH221 preliminary 271 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - reserved: bit 6 - tc rdi-v defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently detecting a remo te defect indicator in bit-0 of the tandem connection frame 7 3 for 5 consecutive frames. this alarm is cleared when no rdi defect indicator is detected in bit-0 of the tandem connection frame 73 for 5 consecutive frames. 0 - indicates that the vt-de-mapper block is not cu rrently detecting a tc rdi-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly detecting a tc rdi-v defect condition. bit 5 - tc odi-v defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently detecting an out going defect indicator in bit-1 of the tandem connection frame 7 4 for 5 consecutive frames. this alarm is cleared when no odi-v defect indicator is detected in bit-1 of the tandem connection frame 74 for 5 consecutive frames. 0 - indicates that the vt-de-mapper block is not cu rrently detecting a tc odi-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly detecting a tc odi-v defect condition. bit 4 - tc api-v message mismatch defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "t andem connection access point identifier message mismatch " defect condition. this defect is declared when a tandem connection api message is accepted that is differen t from the expected tandem connection api message. this defect is cleared when the expected api message is receive d on the j2 byte for n consecutive messages, where n is either 3 or 5 depending on the message acceptance threshol d set for api messages on bit-3 of the channel cont rol - vt-de- mapper path trace buffer control register (vtdptbcr ) on address 0xnd71. 0 - indicates that the vt-de-mapper block is not cu rrently declaring a tc api message mismatch. 1 - indicates that the vt-de-mapper block is curren tly declaring a tc api message mismatch. bit 3 - unstable tc api-v message defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "t andem connection unstable access point identifier message " defect condition. this defect is declared when t he internal tc api unstable message counter has detected 8 or more consecutively different api message. the vt-de-ma pper block will increment the internal tc api unstable message counter for each time that it receives a tandem co nnection api message that differs from the previously received m essage. this defect is cleared when the same api me ssage is received on the j2 byte for n consecutive messages, where n is either 3 or 5 depending on the message acceptance threshold set for api messages on bit-3 of the chan nel control - vt-de-mapper path trace buffer contro l register (vtdptbcr) on address 0xnd71. 0 - indicates that the vt-de-mapper block is not cu rrently declaring a tc unstable api message mismatc h. 1 - indicates that the vt-de-mapper block is curren tly declaring a tc unstable api message mismatch. t able 247: c hannel c ontrol - vt-d e m apper t andem c onnection s tatus r egister (vtdtcsr = 0 x nd62) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved tc rdi defect declared tc odi defect declared tc api message mismatch defect declared unstable tc api message defect declared tc lomf defect declared tc uneq defect declared tc ais defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 272 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 2 - tc lomf-v defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring a "tan dem connection loss of multiframe" defect condition. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the tc lomf-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the tc lomf-v defect condition. bit 1 - tc uneq-v defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently detecting a "tan dem connection unequipped indication signal" defect con dition. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the tc uneq-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the tc uneq-v defect condition. bit 0 - tc ais-v defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently detecting a "tan dem connection alarm indication signal" defect conditio n in the received n2 byte. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the tc ais-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the tc ais-v defect condition.
XRT86SH221 preliminary 273 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:3] - reserved: bit 2 - tim-v defect declared: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "v t trace identification mismatch" (tim-v) defect condition. the vt-de-mapper block will declare the tim-v defec t condition, when none of the received 1, 16 or 64- byte string (received via the j2 byte, within the incoming vt-d ata-stream) matches the expected 1, 16 or 64 byte m essage. the vt-de-mapper block will clear the "tim-v" defec t condition, when 80% of the received 1, 16 or 64 b yte string (received via the j2 byte) matches the 1, 16 or 64 byte message. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the tim-v defect condition. 1 - indicates that the vt-de-mapper block is curren tly declaring the tim-v defect condition. bit 1 - vt path trace message unstable defect decla red: this read-only bit-field indicates whether or not t he vt-de-mapper block is currently declaring the "v t path trace message unstable" defect condition. the vt-de-mapp er block will declare the "vt path trace message un stable" defect condition, whenever the "vt path trace messa ge unstable" counter reaches the value "8". the vt -de-mapper block will increment the "vt path trace message uns table" counter for each time that it receives a "vt path trace message" that differs from the previously received message. the "vt path trace message unstable" coun ter is cleared to "0" whenever the vt-de-mapper block has received a given "vt path trace message" 3 (or 5) consecuti ve times. 0 - indicates that the vt-de-mapper block is not cu rrently declaring the "vt:path trace message unstab le" defect condition. 1 - indicates that the vt de-mapper block is curren tly declaring the "vt path trace message unstable" defect condition. n ote : the vt-de-mapper block will also set this bit-field "0" anytime it receives a given "vt path trace mes sage" 3 (or 5) consecutive times. bit 0 - reserved: t able 248: c hannel c ontrol - vt-d e m apper j2 b yte s tatus r egister (vtdj2bsr = 0 x nd63) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved tim-v defect declared vt path trace message unstable defect declared reserved r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 274 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:2] - reserved: bit 1 - change of receive aps value interrupt: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of receive aps value" interrupt since the last read of this register. the vt-de-mapper block will genera te this interrupt whenever it has "accepted" a new "aps" value (from the k4 bytes within the incoming vt-data-stream). 0 - indicates that the "change of receive aps value " interrupt has not occurred since the last read of this register. 1 - indicates that the "change of receive aps value " interrupt has occurred since the last read of thi s register. bit 0 - transmit or receive elastic store overflow event interrupt: this reset-upon-read bit-field indicates whether or not the "vt mapper/vt-de-mapper" block has generat ed the "elastic store overflow event" interrupt since the last read of this register. the vt-mapper/de-mappe r block will generate this interrupt in response to either of th e following conditions. ? whenever the "transmit fifo" within the vt-mapper b lock, experiences an overflow event. ? whenever the "receive fifo" within the vt-de-mapper block, experiences an overflow event. 0 - indicates that the channel has not generated an "elastic store overflow" interrupt since the last read of this register. 1 - indicates that the channel has generated an "el astic store overflow" interrupt since the last read of this register. t able 249: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 1 (vtdcsr1 = 0 x nd64) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of receive aps value- composite elastic store overflow event composite r/o r/o r/o r/o rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 275 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - vt size error interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "vt size error" interrupt since the last read of this register. th e vt-de-mapper block will generate the "vt size err or" interrupt anytime it declares the "vt size error" defect condition. 0 - indicates that the vt size error interrupt has not occurred since the last read of this register. 1 - indicates that the vt size error interrupt has occurred since the last read of this register. bit 6 - change of lop-v defect condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of lop-v defect condition" interrupt since the last re ad of this register. the vt-de-mapper block will g enerate this interrupt in response to either of the following co nditions. ? whenever the vt-de-mapper block declares the lop-v defect condition. ? whenever the vt-de-mapper block clears the lop-v de fect condition. 0 - indicates that the "change of lop-v defect cond ition" interrupt has not occurred since the last re ad of this register. 1 - indicates that the "change of lop-v defect cond ition" interrupt has occurred since the last read o f this register. bit 5 - change of rfi-v defect condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of rfi-v defect condition" interrupt since the last re ad of this register. the vt-de-mapper block will g enerate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the rfi-v defect condition ? whenever the vt-de-mapper block clears the rfi-v de fect condition. 0 - indicates that the "change of rfi-v defect cond ition" interrupt has not occurred since the last re ad of this register. 1 - indicates that the "change of rfi-v defect cond ition" interrupt has occurred since the last read o f this register. bit 4 - change of rdi-v defect condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of rdi-v defect condition" interrupt since the last re ad of this register. the vt-de-mapper block will g enerate this interrupt in response to either of the following co nditions. ? whenever the vt-de-mapper block declares the rdi-v defect condition. ? whenever the vt-de-mapper block clears the rdi-v de fect condition. 0 - indicates that the "change of rdi-v defect cond ition" interrupt has not occurred since the last re ad of this register. 1 - indicates that the "change of rdi-v defect cond ition" interrupt has occurred since the last read o f this register. t able 250: c hannel c ontrol - vt-d e m apper c omposite s tatus r egister 0 (vtdcsr0 = 0 x nd65) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 vt size error interrupt status change of lop-v defect condition interrupt status change of rfi-v defect condition interrupt status change of rdi-v defect condition interrupt status change of ais-v failure condition interrupt status change of ais-v defect condition interrupt status change of vt label interrupt status change of e1 ais defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 276 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 3 - change of ais-v failure condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of ais-v failure condition" interrupt since the last r ead of this register. the vt-de-mapper block will generate this interrupt in response to either of the following co nditions. ? whenever the vt-de-mapper block declares the ais-v failure condition. ? whenever the vt-de-mapper block clears the ais-v fa ilure condition. 0 - indicates that the "change of ais-v failure con dition" interrupt has not occurred since the last r ead of this register. 1 - indicates that the "change of ais-v failure con dition" interrupt has occurred since the last read of this register. bit 2 - change of ais-v defect condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of ais-v defect condition" interrupt since the last re ad of this register. the vt-de-mapper block will g enerate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the ais-v defect condition. ? whenever the vt-de-mapper block clears the ais-v de fect condition. 0 - indicates that the "change of ais-v defect cond ition" interrupt has not occurred since the last re ad of this register. 1 - indicates that the "change of ais-v defect cond ition" interrupt has occurred since the last read o f this register. bit 1 - change of vt label value interrupt status this reset-upon-read bit-field indicates whether or not the "change of vt label value" interrupt has o ccurred since the last read of this register. the vt-de-mapper b lock will generate this interrupt anytime it has "a ccepted" a new vt label value (that it has received via the v5 byte w ithin the incoming vt data-stream). 0 - indicates that the "change of vt label value" i nterrupt has not occurred since the last read of th is register. 1 - indicates that the "change of vt label value" i nterrupt has occurred since the last read of this r egister. bit 0 - change of e1 ais defect condition interrupt status this reset-upon-read bit-field indicates whether or not the "change of e1 ais defect condition" interr upt has occurred since the last read of this register. the vt-mapper block will generate this interrupt in re sponse to any one of the following conditions. ? whenever the vt-mapper block declares the e1 ais de fect (with the ingress direction e1 traffic). ? whenever the vt-mapper block clears the e1 ais defe ct (within the ingress direction e1 traffic). 0 - indicates that the "change of e1 ais defect con dition" interrupt has not occurred since the last r ead of this register. 1 - indicates that the "change of e1 ais defect con dition" interrupt has occurred since the last read of this register.
XRT86SH221 preliminary 277 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - reserved: bit 6 - change of tc rdi-v defect interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of tandem connection remote defect indicator condition " interrupt since the last read of this register. the vt-de- mapper block will generate this interrupt in respon se to either of the following conditions. ? whenever the vt-de-mapper block declares the tc rdi -v defect condition. ? whenever the vt-de-mapper block clears the tc rdi-v defect condition. 0 - indicates that the "change of tc rdi-v defect c ondition" interrupt has not occurred since the last read of this register. 1 - indicates that the "change of tc rdi-v defect c ondition" interrupt has occurred since the last rea d of this register. bit 5 - change of tc odi-v defect interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of tandem connection outgoing defect indicator conditi on" interrupt since the last read of this register. the vt-de- mapper block will generate this interrupt in respon se to either of the following conditions. ? whenever the vt-de-mapper block declares the tc odi -v defect condition. ? whenever the vt-de-mapper block clears the tc odi-v defect condition. 0 - indicates that the "change of tc odi-v defect c ondition" interrupt has not occurred since the last read of this register. 1 - indicates that the "change of tc odi-v defect c ondition" interrupt has occurred since the last rea d of this register. bit 4 - change of tc api-v message mismatch defect interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of tandem connection access point identifier message m ismatch condition" interrupt since the last read of this register. the vt-de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the tc api -v message mismatch defect condition. ? whenever the vt-de-mapper block clears the tc api-v message mismatch defect condition. 0 - indicates that the "change of tc api-v message mismatch defect condition" interrupt has not occurr ed since the last read of this register. 1 - indicates that the "change of tc api-v message mismatch defect condition" interrupt has occurred s ince the last read of this register. t able 251: c hannel c ontrol - vt-d e m apper t andem c onnection i nterrupt s tatus r egister (vtdtcisr = 0 x nd66) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved tc rdi defect interrupt status tc odi defect interrupt status tc api message mismatch defect interrupt status unstable tc api message defect interrupt status tc lomf interrupt status tc uneq defect interrupt status tc ais defect interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH221 278 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 3 - change of unstable tc api-v message defect interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of unstable tandem connection access point identifier message defect condition" interrupt since the last read of this register. the vt-de-mapper block will generate thi s interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the unstab le tc api-v message defect condition. ? whenever the vt-de-mapper block clears the unstable tc api-v message defect condition. 0 - indicates that the "change of unstable tc api-v message defect condition" interrupt has not occurr ed since the last read of this register. 1 - indicates that the "change of unstable tc api-v message defect condition" interrupt has occurred s ince the last read of this register. bit 2 - change of tc lomf-v interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of tandem connection loss of multiframe defect conditi on" interrupt since the last read of this register. the vt-de- mapper block will generate this interrupt in respon se to either of the following conditions. ? whenever the vt-de-mapper block declares the tc lom f-v defect condition. ? whenever the vt-de-mapper block clears the tc lomf- v defect condition. 0 - indicates that the "change of tc lomf-v defect condition" interrupt has not occurred since the las t read of this register. 1 - indicates that the "change of tc lomf-v defect condition" interrupt has occurred since the last re ad of this register. bit 1 - change of tc uneq-v defect interrupt status : this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of tandem connection unequipped indication signal cond ition" interrupt since the last read of this regist er. the vt-de- mapper block will generate this interrupt in respon se to either of the following conditions. ? whenever the vt-de-mapper block declares the tc une q-v defect condition. ? whenever the vt-de-mapper block clears the tc uneq- v defect condition. 0 - indicates that the "change of tc uneq-v defect condition" interrupt has not occurred since the las t read of this register. 1 - indicates that the "change of tc uneq-v defect condition" interrupt has occurred since the last re ad of this register. bit 0 - change of tc ais-v defect interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of tandem connection alarm indication signal defect co ndition" interrupt since the last read of this regi ster. the vt-de- mapper block will generate this interrupt in respon se to either of the following conditions. ? whenever the vt-de-mapper block declares the tc ais -v defect condition. ? whenever the vt-de-mapper block clears the tc ais-v defect condition. 0 - indicates that the "change of tc ais-v defect c ondition" interrupt has not occurred since the last read of this register. 1 - indicates that the "change of tc ais-v defect c ondition" interrupt has occurred since the last rea d of this register.
XRT86SH221 preliminary 279 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:6] - reserved: bit 5 - change of vt path trace message unstable de fect condition interrupt status: this reset-upon-read bit-field indicates whether or not the "change of vt path trace message unstable defect condition" interrupt has occurred since the last re ad of this register. the vt-de-mapper block will g enerate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the "vt pa th trace message unstable" defect condition. ? whenever the vt de-mapper block clears the "vt path trace message unstable" defect condition. 0 - indicates that the "change of vt path trace mes sage unstable defect condition" interrupt has not o ccurred since the last read of this register. 1 - indicates that the "change of vt path trace mes sage unstable defect condition" interrupt has occur red since the last read of this register. bit 4 - new vt path trace message interrupt status: this reset-upon-read bit-field indicates whether or not the "new vt path trace message" interrupt has occurred since the last read of this register. the vt-de-ma pper block will generate this interrupt whenever it has "accepted" a new "vt path trace message" via the incoming vt-dat a-stream. 0 - indicates that the "new vt path trace message" interrupt has not occurred since the last read of t his register. 1 - indicates that the "new vt path trace message" interrupt has occurred since the last read of this register. bit 3 - change of tim-v defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "ch ange of tim-v defect condition" interrupt since the last re ad of this register. the vt-de-mapper block will g enerate this interrupt in response to either of the following co nditions. ? whenever it declares the tim-v defect condition. ? whenever it clears the tim-v defect condition. 0 - indicates that the "change of tim-v defect cond ition" interrupt has not occurred since the last re ad of this register. 1 - indicates that the "change of tim-v defect cond ition" interrupt has occurred since the last read o f this register. bit [2:0] - reserved: t able 252: c hannel c ontrol - vt-d e m apper i nterrupt s tatus r egister 0 (vtdisr0 = 0 x nd67) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of vt path trace message unstable defect condition interrupt status new vt path trace message interrupt status change of tim-v defect condition interrupt status reserved r/o r/o rur rur rur r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 280 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:2] - reserved: bit 1 - change of receive aps value interrupt enabl e: this read/write bit-field permits the user to eithe r enable or disable the "change of receive aps valu e" interrupt. if the user enables this interrupt, then the vt-de- mapper block will generate this interrupt anytime i t has "accepted" a new aps value (via the k4 byte within the incoming vt-data-stream). 0 - disables the "change of receive aps value" inte rrupt. 1 - enables the "change of receive aps value" inter rupt. bit 0 - transmit or receive elastic store overflow event interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "elastic store overflow eve nt" interrupt. if the user enables this interrupt, then the channel w ill generate this interrupt in response to either o f the following conditions. ? whenever the "transmit fifo" within the vt-mapper b lock, experiences an overflow event. ? whenever the "receive fifo" within the vt-de-mapper block, experiences an overflow event. 0 - disables the "elastic store overflow event" int errupt. 1 - enables the "elastic store overflow event" inte rrupt. t able 253: c hannel c ontrol - vt-d e m apper i nterrupt e nable r egister 2 (vtdier2 = 0 x nd68) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of receive aps value interrupt enable elastic store overflow event interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 281 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - vt size error interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "vt size error" interrupt. if the user enables this interrupt, then the "vt-de-mapper" block will generate this interrupt anytime it declares the "vt size error" defect condition. 0 - disables the "vt size error" interrupt. 1 - enables the "vt size error" interrupt. bit 6 - change of lop-v defect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of lop-v defect con dition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the lop-v defect condition. ? whenever it clears the lop-v defect condition. 0 - disables the "change of lop-v defect condition" interrupt. 1 - enables the "change of lop-v defect condition" interrupt. bit 5 - change of rfi-v defect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of rfi-v defect con dition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the rfi-v defect condition. ? whenever it clears the rfi-v defect condition. 0 - disables the "change of rfi-v defect condition" interrupt. 1 - enables the "change of rfi-v defect condition" interrupt. bit 4 - change of rdi-v defect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of rdi-v defect con dition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the rdi-v defect condition. ? whenever it clears the rdi-v defect condition. 0 - disables the "change of rdi-v defect condition" interrupt. 1 - enables the "change of rdi-v defect condition" interrupt. t able 254: c hannel c ontrol - vt-d e -m apper i nterrupt e nable r egister 1 (vtdier1 = 0 x nd69) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 vt size error interrupt enable change of lop-v defect condition interrupt enable change of rfi-v defect condition interrupt enable change of rdi-v defect condition interrupt enable change of ais-v failure condition interrupt enable change of ais-v defect condition interrupt enable change of vt label interrupt enable change of e1 ais defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 282 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 3 - change of ais-v failure condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of ais-v failure co ndition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the ais-v failure condition. ? whenever it clears the ais-v failure condition. 0 - disables the "change of ais-v failure condition " interrupt. 1 - enables the "change of ais-v failure condition" interrupt. bit 2 - change of ais-v defect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of ais-v defect con dition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the ais-v defect condition. ? whenever it clears the ais-v defect condition. 0 - disables the "change of ais-v defect condition" interrupt. 1 - enables the "change of ais-v defect condition" interrupt. bit 1 - change of vt label value interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of vt label value" interrupt. if the user enables this interrupt, then the "vt-de-mapper " block will generate this interrupt anytime it has "accepted" a new "vt label value" via the v5 bytes within the incomi ng vt-data-stream. 0 - disables the "change of vt label value" interru pt. 1 - enables the "change of vt label value" interrup t. bit 0 - change of e1 ais defect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of e1 ais defect co ndition" interrupt. if the user enables this interrupt, the n the "vt-mapper" block will generate this interrup t in response to either of the following events. ? whenever it declares the e1 ais defect condition. ? whenever it clears the e1 ais defect condition. 0 - disables the "change of e1 ais defect condition " interrupt. 1 - enables the "change of e1 ais defect condition" interrupt.
XRT86SH221 preliminary 283 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - reserved: bit 6 - change of tc rdi-v defect condition interru pt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of tc rdi-v defect condition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the tc rdi-v defect condition. ? whenever it clears the tc rdi-v defect condition. 0 - disables the "change of tc rdi-v defect conditi on" interrupt. 1 - enables the "change of tc rdi-v defect conditio n" interrupt. bit 5 - change of tc odi-v defect condition interru pt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of tc odi-v defect condition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the tc odi-v defect condition. ? whenever it clears the tc odi-v defect condition. 0 - disables the "change of tc odi-v defect conditi on" interrupt. 1 - enables the "change of tc odi-v defect conditio n" interrupt. bit 4 - change of tc api-v message mismatch conditi on interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of tc api-v message mismatch condition" interrupt. if the user enables this int errupt, then the "vt-de-mapper" block will generate this interrupt in response to either of the following conditions. ? whenever it declares the tc api-v message mismatch condition. ? whenever it clears the tc api-v message mismatch co ndition. 0 - disables the "change of tc api-v message mismat ch condition" interrupt. 1 - enables the "change of tc api-v message mismatc h condition" interrupt. bit 3 - change of unstable tc api-v message defect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of unstable tc api- v message defect condition" interrupt. if the user enables t his interrupt, then the "vt-de-mapper" block will g enerate this interrupt in response to either of the following conditions. ? whenever it declares the unstable tc api-v message defect condition. ? whenever it clears the unstable tc api-v message de fect condition. 0 - disables the "change of unstable api-v message defect condition" interrupt. 1 - enables the "change of unstable api-v message d efect condition" interrupt. t able 255: c hannel c ontrol - vt-d e -m apper t andem c onnection i nterrupt e nable r egister (vtdtcier = 0 x nd6a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved tc rdi defect interrupt enable tc odi defect interrupt enable tc api message mismatch defect interrupt enable unstable tc api message defect interrupt enable tc lomf interrupt enable tc uneq defect interrupt enable tc ais defect interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 284 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 2 - change of tc lomf-v defect condition interr upt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of tc lomf-v defect condition" interrupt. if the user enables this interrupt, the n the "vt-de-mapper" block will generate this inter rupt in response to either of the following conditions. ? whenever it declares the tc lomf-v defect condition . ? whenever it clears the tc lomf-v defect condition. 0 - disables the "change of tc lomf-v defect condit ion" interrupt. 1 - enables the "change of tc lomf-v defect conditi on" interrupt. bit 1 - change of tc uneq-v indication signal condi tion interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of tc uneq-v indica tion signal condition" interrupt. if the user enables this int errupt, then the "vt-mapper" block will generate th is interrupt in response to either of the following events. ? whenever it declares the tc uneq-v indication signa l condition. ? whenever it clears the tc uneq-v indication signal condition. 0 - disables the "change of tc uneq-v indication si gnal" interrupt. 1 - enables the "change of tc uneq-v indication sig nal" interrupt. bit 0 - change of tc ais-v defect condition interru pt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of tc ais-v defect condition" interrupt. if the user enables this interrupt, the n the "vt-mapper" block will generate this interrup t in response to either of the following events. ? whenever it declares the tc ais-v defect condition. ? whenever it clears the tc ais-v defect condition. 0 - disables the "change of tc ais-v defect conditi on" interrupt. 1 - enables the "change of tc ais-v defect conditio n" interrupt.
XRT86SH221 preliminary 285 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:6] - reserved: bit 5 - change of vt path trace message unstable de fect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of vt path trace me ssage unstable defect condition" interrupt. if the user enables this interrupt, then the vt-de-mapper block will generate this interrupt in response to either of the following ev ents. ? whenever the vt-de-mapper block declares the "vt-pa th trace message unstable" defect condition. ? whenever the vt-de-mapper block clears the "vt-path trace message unstable" defect condition. 0 - disables the "change of vt path trace message u nstable defect condition" interrupt. 1 - enables the "change of vt path trace message un stable defect condition" interrupt. bit 4 - new vt path trace message interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "new vt path trace message" interrupt. if the user enables this interrupt, then the vt-de-map per block will generate this interrupt whenever it has "accepted" a new "vt path trace message" via the incoming vt-dat a-stream. 0 - disables the "new vt path trace message" interr upt. 1 - enables the "new vt path trace message" interru pt. bit 3 - change of tim-v defect condition interrupt enable: this read/write bit-field permits the user to eithe r enable or disable the "change of tim-v defect con dition" interrupt. if the user enables this interrupt, the n the vt-de-mapper block will generate this interru pt in response to either of the following events. ? whenever it declares the tim-v defect condition. ? whenever it clears the tim-v defect condition. 0 - disables the "change of tim-v defect condition" interrupt. 1 - enables the "change of tim-v defect condition" interrupt. bit [2:0] - reserved: t able 256: c hannel c ontrol - vt-d e -m apper i nterrupt e nable r egister 0 (vtdier0 = 0 x nd6b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of vt path trace message unstable defect condition interrupt enable new vt path trace message interrupt enable change of tim-v defect condition interrupt enable reserved r/o r/o r/w r/w r/w r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH221 286 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - received tc enable[1:0]: these two read/write bit-fields are used to enable the tandem connection feature in the vt demapper. the vt path trace message length [1:0] on bit-1 and bit-0 must be set to the value "0x01" or "0x00" depending on the expected 16 bytes or 1 byte message length. the relationship between the contents of these bit- fields and the corresponding receive tandem connect ion messaging type is presented below. bit 5 - reserved: bit 4 - received vt path trace message buffer selec t: this read/write bit-field permits a user to specify which of the following "receive vt path trace mess age" buffer segments that the microprocessor will read out when ever it reads out the contents of the receive path trace message buffer. ? a.the "actual" receive vt path trace message buffer . the "actual" receive vt path trace message buffe r contains the contents of the most recently received (and accepted) vt path trace messages via the inco ming vt-data-stream. ? b.the "expected" receive vt path trace message buff er. the "expected" receive path trace message buffer contains the contents of the "vt path trace message" that the user "expects" to receive. the c ontents of this particular buffer are usually specified by the user. 0 - configures the chip to return the contents of t he "actual" receive vt path trace message" buffer, whenever the user executes a read to the "receive vt path trace message" buffer. 1 - configures the chip to return the contents of t he "expected" receive vt path trace message" buffer , whenever the user executes a read to the "receive vt path tr ace message" buffer. bit 3 - receive vt path trace message accept thresh old: this read/write bit-field permits a user to select the number of consecutive times that the "vt-de-map per" block must receive a given "vt path trace message" before it is "validated" and loaded into the "actual" rec eive vt path trace message buffer, as described below. 0 - configures the vt-de-mapper block to "validate" the incoming vt path trace message after it has re ceived it the t able 257: c hannel c ontrol - vt-d e -m apper p ath t race b uffer c ontrol r egister (vtdptbcr = 0 x nd71) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive tc enable [1:0] reserved receive vt path trace message buffer select vt path trace mes- sage accept threshold vt path trace message type vt path trace message length[1:0] r/w r/w rur rur rur r/o r/o r/o 0 0 0 0 0 0 0 0 r eceive tc e nable [1:0] r eceive t andem c onnection o peration 00 tandem connection feature is disabled. 01 tandem connection enabled for 16-byte messaging o peration. the n2 byte messaging memory buffer segment is shared with the j2 64-byte memory buffer. 16-bytes message length must be sel ected using the appropriate values written on vt path trace message length[1:0] bit-1 and bit-0. 10 reserved. 11 tandem connection enabled for 1-byte messaging op eration. 1-byte message length must be selected using the appropria te values written on vt path trace message length[1:0] bit-1 and bit-0.
XRT86SH221 preliminary 287 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 third time in succession. 1 - configures the vt-de-mapper block to "validate" the incoming vt path trace message after it has re ceived it the fifth time in succession. bit 2 - receive vt path trace message type: this read/write bit-field permits the user to speci fy how the "vt-de-mapper" block will locate the bou ndary of the incoming vt path trace message (within the incoming vt-data-stream) as depicted below. 0 - configures the vt-de-mapper block to expect the "vt path trace message" boundary to be denoted by a "line feed" character. 1 - configures the vt-de-mapper block to except the "vt path trace message" boundary to be denoted by the presence of a "1" in the "msb" (most significant bi t) of the first byte (within the incoming vt path t race message). in this case, all of the remaining bytes (within the i ncoming vt path trace message) will each have a "0" within their msbs. bit [1:0] - vt path trace message length[1:0]: these read/write bit-fields permit the user to spec ify the length of the "receive vt path trace messag e that the "vt-de-mapper" block will accept and load into the "actual" receive vt path trace message buffer. the relationship between the contents of these bit-fields and the co rresponding "receive vt path trace message" length is presented below. vt p ath t race m essage l ength [1:0] r esulting vt p ath t race m essage l ength (b ytes ) 00 1 01 16 1x 64
preliminary XRT86SH221 288 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - reserved: bit 5 - auto transmit ais-v upon ais-v defect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the ais-v defect condition within the i ncoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the ais-v defect cond ition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the ais-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 4 - auto transmit ais-v upon uneq-v defect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the uneq-v defect condition within the incoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the uneq-v defect con dition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the uneq-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 3 - reserved: bit 2 - auto transmit ais-v upon lop-v defect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the lop-v defect condition within the i ncoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the lop-v defect cond ition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the lop-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. t able 258: c hannel c ontrol - vt-d e -m apper a uto ais c ontrol r egister 1 (vtdaaiscr1 = 0 x nd72) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved auto transmit ais-v upon ais-v defect auto transmit ais-v upon uneq-v defect reserved auto transmit ais-v upon lop-v defect auto transmit ais-v upon plm-v defect reserved r/o r/o r/w r/w r/o r/w r/w r/o 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 289 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 1 - auto transmit ais-v upon plm-v defect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the plm-v defect condition within the i ncoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the plm-v defect cond ition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the plm-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 0 - reserved:
preliminary XRT86SH221 290 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - auto transmit ais-v upon vt path trace mess age unstable defect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the vt path trace message unstable defe ct condition within the incoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the vt path trace mes sage unstable defect condition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the vt path trace message unst able defect condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 6 - auto transmit ais-v upon tim-v defect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the tim-v defect condition within the i ncoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the tim-v defect cond ition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the tim-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 5 - auto transmit ais-v upon n1 byte alarm defe ct: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it detects an all "0" value on the received n1 byte and declares the n1 byte alarm defect condition wi thin the incoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the n1 byte alarm def ect condition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the n1 byte alarm defect condi tion. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. t able 259: c hannel c ontrol - vt-d e -m apper a uto ais c ontrol r egister 0 (vtdaaiscr0 = 0 x nd73) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 auto transmit ais-v upon vt path trace message unstable defect auto transmit ais-v upon tim-v defect auto transmit ais-v upon n1 byte alarm defect auto transmit ais-v upon n2 iais bit alarm defect auto transmit ais-v upon tc lomf-v defect auto transmit ais-v upon tc api-v message mismatch defect auto transmit ais-v upon tc uneq-v indication signal detect auto transmit ais-v enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 291 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 4 - auto transmit ais-v upon n2 iais alarm defe ct: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the n2 incoming ais alarm defect condit ion within the incoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the n2 incoming ais alarm defect condition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the n2 incoming ais alarm defe ct condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 3 - auto transmit ais-v upon tc lomf-v alarm de fect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the tc lomf-v defect condition within t he incoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the tc lomf-v defect condition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the tc lomf-v defect condition . n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 2 - auto transmit ais-v upon tc api-v message m ismatch defect: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the tc api-v message mismatch defect co ndition within the incoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the tc api-v message mismatch defect condition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the tc api-v message mismatch defect condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition. bit 1 - auto transmit ais-v upon tc uneq-v indicati on signal condition: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit e1 liu block), anytime (and f or the duration that) it declares the tc uneq-v indication signal conditi on within the incoming vt-data-stream. 0 - does not configure the vt-de-mapper block to au tomatically transmit the ais-v indicator (via the " downstream" traffic) whenever it declares the tc uneq-v indicat ion signal condition. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am" traffic) whenever it declares the tc uneq-v indication signa l condition. n ote : the user must also set bit 0 (auto transmit ais-v e nable) within the "channel control - vt-de-mapper b lock - egress direction - receive vt auto ais control" reg ister to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in r esponse to this defect condition.
preliminary XRT86SH221 292 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 0 - auto transmit ais-v enable: this read/write bit-field permits the user to confi gure the vt-de-mapper block to automatically transm it the ais-v indicator (via the down-stream traffic) whenever (a nd for the duration that) it declares either the ai s-v, lop-v, tim-v, uneq-v, plm-v or "vt path trace message unstable" d efect conditions. 0 - configures the vt-de-mapper block to not automa tically transmit the ais-v indicator (via the "down stream traffic) upon declaration of any of the "above-ment ioned" defect conditions. 1 - configures the vt-de-mapper block to automatica lly transmit the ais-v indicator (via the "downstre am traffic) upon declaration of any of the "above-mentioned" de fect conditions. n ote : the user must also set the corresponding bit-fields (within this register) to "1" in order to configur e the vt-de- mapper block to automatically transmit the ais-v in dicator upon detection of a given alarm/defect cond ition.
XRT86SH221 preliminary 293 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:0] - transmit j2 byte value[7:0]: these read/write bit-fields permit the user to have software control over the value of the j2 byte, wi thin the outbound vt data-stream. if the user configures the vt-mapper block to use t his register as the source of the j2 byte, then it will automatically write the contents of this register into the j2 byt e location, within each "outbound" vt multi-frame. this feature is enabled whenever the user writes th e value "[1, 0]" into bits 1 and 0 (transmit vt-pat h trace message source[1:0]) within the "channel control - vt mappe r block - ingress direction - vt path trace message control" register. bit [7:0] - transmit n2 byte value[7:0]: these read/write bit-fields permit the user to have software control over the value of the n2 byte, wi thin the outbound vt data-stream. the vt-mapper block will (unconditionally) use this register as the source of the n2 byte, then it wil l automatically write the contents of this register into the n2 byte loca tion, within each "outbound" vt multi-frame. t able 260: c hannel c ontrol - vt-m apper t ransmit j2 b yte v alue r egister (vtmj2vr = 0 x nd76) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit j2 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 261: c hannel c ontrol - vt-m apper t ransmit n2 b yte v alue r egister (vtmn2vr = 0 x nd77) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit n2 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 294 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:6] - transmit tc enable[1:0]: these read/write bit-fields are used to enable the tandem connection feature in the vt mapper. the vt path trace message length [1:0] on bit-3 and bit-2 must be set to the value "0x00" or "0x01" depending on t he desired 1- byte or 16-bytes message length. the relationship between the contents of these bit- fields and the corresponding transmit tandem connec tion messaging type is presented below. bit 5 - transmit iais bit: this read/write bit-field contain the value that wi ll be written on the incoming ais bit on bit-4 of t he transmitted n2 byte. 0 - the bit value "0" will be transmitted on bit-4 of the transmitted n2 byte. 1 - the bit value "1" will be transmitted on bit-4 of the transmitted n2 byte. bit 4 - reserved: t able 262: c hannel c ontrol - vt-m apper t ransmit p ath t race m essage c ontrol r egister (vtmptmcr = 0 x nd79) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit tc enable[1:0] transmit iais reserved transmit vt path trace message length[1:0] transmit vt path trace message source[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t ransmit tc e nable [1:0] t ransmit t andem c onnection o peration 00 tandem connection feature is disabled. the n2 by te transmitted is the value written on n2 byte software register 0xnd77. 01 tandem connection enabled for 16-bytes messaging operation. the n2 byte messaging memory buffer segment is shared with the j2 64-byte memory buffer. the written value is transmitted al ong with the multiframe alignment pattern, and tc odi and tc rdi. 16-bytes message length must be selected using the appropriate values writt en on vt path trace message length[1:0] bit-3 and bit-2. 10 reserved. 11 tandem connection enabled for 1-byte messaging op eration. the n2 byte transmitted is the value written on n2 byte so ftware register 0xnd77. the written value is transmitted along with the mul tiframe alignment pat- tern, and tc odi and tc rdi. 1-byte message length must be selected using the appropriate values written on vt path tra ce message length[1:0] bit-3 and bit-2.
XRT86SH221 preliminary 295 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [3:2] - transmit vt path trace message length[1 :0]: these read/write bit-fields permit the user to spec ify the length of the vt path trace message that th e vt-mapper block will repeatedly transmit to the remote vt pte . the relationship between the contents of these b it-fields and the corresponding vt path trace message length is prese nted below. bit [1:0] - transmit vt path trace message source[1 :0]: these read/write bit-fields permit the user to spec ify the source of the "outbound" vt path trace mess age that will transported via the j2 byte channel (within the out bound vt-data-stream) as depicted below. t ransmit vt p ath t race m essage l ength [1:0] r esulting vt p ath t race m essage b yte l ength 00 1 byte 01 16 bytes 1x 64 bytes t ransmit vt p ath t race m essage s ource [1:0] r esulting s ource of the vt p ath t race m essage 00 fixed value: the vt-mapper block will automatically set the j2 b yte, within the each outbound vt-multi-frame to the value "0x01". 01 the transmit vt path trace message buffer: the vt-mapper block will read out the contents with in the "transmit vt-path trace message" buffer, and will transmit th is message to the remote vt pte. 10 from the "transmit j2 byte value[7:0]" register: in this setting, the vt-mapper block will read out the contents of the "transmit j2 byte value register, and will insert t his value into the j2 byte-position within each outbound vt-multi-frame. 11 do not use
preliminary XRT86SH221 296 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:2] - reserved: bit 1 - transmit tc uneq-v with bip-2 enable: these read/write bit-fields are used to enable the transmission of the tandem connection unequipped in dication signal and the 2-bit bit interleave parity feature in the vt mapper. 0 - disables the transmission of tc uneq-v. 1 - enables the transmission of tc uneq-v with the generation of tc bip-2. bit 0 - transmit tc uneq-v enable: these read/write bit-fields are used to enable the transmission of the tandem connection unequipped in dication signal feature in the vt mapper. 0 - disables the transmission of tc uneq-v. 1 - enables the transmission of tc uneq-v without t he generation of tc bip-2. t able 263: c hannel c ontrol - vt-m apper t ransmit n2 c ontrol r egister (vtmn2cr = 0 x nd7b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved transmit tc uneq-v with tc bip-2 enable transmit tc uneq-v enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 297 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:3] - reserved: bit 2 - transmit tc rdi-v upon ais-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the ais-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the ais-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the ais-v defect co ndition. bit 1 - transmit tc rdi-v upon lop-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the lop-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the lop-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the lop-v defect co ndition. bit 0 - transmit tc rdi-v upon uneq-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the uneq- v indication signal condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the uneq-v in dication signal condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the uneq-v indicati on signal condition. t able 264: c hannel c ontrol - vt-m apper t ransmit t andem c onnection rdi-v c ontrol r egister 1 (vtmtcrdicr1 = 0 x nd7e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved transmit tc rdi-v upon ais-v defect transmit tc rdi-v upon lop-v defect transmit tc rdi-v upon uneq-v detect r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 298 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - transmit tc rdi-v upon plm-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the plm-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the plm-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the plm-v defect co ndition. bit 6 - transmit tc rdi-v upon tim-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tim-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tim-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tim-v defect co ndition. bit 5 - transmit tc rdi-v upon vt path trace messag e unstable defect: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the vt pa th trace message unstable defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the vt path t race message unstable defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the vt path trace m essage unstable defect condition. bit 4 - transmit tc rdi-v upon tc lomf-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc lo mf-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc lomf-v defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc lomf-v defec t condition. t able 265: c hannel c ontrol - vt-m apper t ransmit t andem c onnection rdi-v c ontrol r egister 0 (vtmtcrdicr0 = 0 x nd7f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit tc rdi-v upon plm-v defect transmit tc rdi-v upon tim-v defect transmit tc rdi-v upon vt path trace message unstable defect transmit tc rdi-v upon tc lomf-v defect transmit tc rdi-v upon tc uneq-v detect transmit tc rdi-v upon iais defect transmit tc rdi-v upon tc api-v message mismatch defect transmit tc rdi-v upon tc api-v message unstable defect r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 299 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 3 - transmit tc rdi-v upon tc uneq-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc un eq-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc uneq-v defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc uneq-v defec t condition. bit 2 - transmit tc rdi-v upon incoming ais-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block detects the incomi ng ais-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block detects the incoming a is defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block detects the incoming ais def ect condition. bit 1 - transmit tc rdi-v upon tc api-v message mis match: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc ap i-v message mismatch defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc api-v message mismatch defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc api-v messag e mismatch defect condition. bit 0 - transmit tc rdi-v upon tc api-v message uns table defect: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection rdi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc ap i-v message unstable defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection rdi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc api-v message unstable defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection rdi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc api-v messag e unstable defect condition.
preliminary XRT86SH221 300 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:3] - reserved: bit 2 - transmit tc odi-v upon ais-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the ais-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the ais-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the ais-v defect co ndition. bit 1 - transmit tc odi-v upon lop-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the lop-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the lop-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the lop-v defect co ndition. bit 0 - transmit tc odi-v upon uneq-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the uneq- v indication signal condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the uneq-v in dication signal condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the uneq-v indicati on signal condition. t able 266: c hannel c ontrol - vt-m apper t ransmit t andem c onnection odi-v c ontrol r egister 1 (vtmtcodicr1 = 0 x nd82) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved transmit tc odi-v upon ais-v defect transmit tc odi-v upon lop-v defect transmit tc odi-v upon uneq-v detect r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 301 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 7 - transmit tc odi-v upon plm-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the plm-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the plm-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the plm-v defect co ndition. bit 6 - transmit tc odi-v upon tim-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tim-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tim-v def ect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tim-v defect co ndition. bit 5 - transmit tc odi-v upon vt path trace messag e unstable defect: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the vt pa th trace message unstable defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the vt path t race message unstable defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the vt path trace m essage unstable defect condition. bit 4 - transmit tc odi-v upon tc lomf-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc lo mf-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc lomf-v defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc lomf-v defec t condition. t able 267: c hannel c ontrol - vt-m apper t ransmit t andem c onnection odi-v c ontrol r egister 0 (vtmtcodicr0 = 0 x nd83) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit tc odi-v upon plm-v defect transmit tc odi-v upon tim-v defect transmit tc odi-v upon vt path trace message unstable defect transmit tc odi-v upon tc lomf-v defect transmit tc odi-v upon tc uneq-v detect transmit tc odi-v upon iais defect transmit tc odi-v upon tc api-v message mismatch defect transmit tc odi-v upon tc api-v message unstable defect r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 302 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 3 - transmit tc odi-v upon tc uneq-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc un eq-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc uneq-v defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc uneq-v defec t condition. bit 2 - transmit tc odi-v upon incoming ais-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block detects the incomi ng ais-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block detects the incoming a is defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block detects the incoming ais def ect condition. bit 1 - transmit tc odi-v upon tc api-v message mis match: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc ap i-v message mismatch defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc api-v message mismatch defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc api-v messag e mismatch defect condition. bit 0 - transmit tc odi-v upon tc api-v message uns table defect: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the tandem connection odi code on the vc2 n2 byte towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tc ap i-v message unstable defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the tandem connection odi code (via t he n2 byte) whenever (and for the duration that) the corr esponding vt-de-mapper block declares the tc api-v message unstable defect condition. 1 - configures the vt-mapper block to automatically transmit the tandem connection odi code (via the n 2 byte) whenever (and for the duration that) the correspond ing vt-de-mapper block declares the tc api-v messag e unstable defect condition.
XRT86SH221 preliminary 303 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:4] - reserved: bit [3:1] - plm-v rdi code[2:0]: these three read/write bit-field permits the user t o specify the value that the vt-mapper block will t ransmit, within the rdi-v bit-fields of the k4 byte (within each ou tbound vt-frame) whenever (and for the duration tha t) the corresponding vt-de-mapper block detects and declar e the plm-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon plm-v) within this regis ter to "1". bit 0 - transmit rdi-v upon plm-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this re gister) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the p lm-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the rdi code (via the k4 byte) whenev er (and for the duration that) the corresponding vt-de-mapper b lock declares the plm-v defect condition. 1 - configures the vt-mapper block to automatically transmit the rdi code (via the k4 byte) whenever ( and for the duration that) the corresponding vt-de-mapper block declares the plm-v defect condition. t able 268: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 3 (vtmrdicr3 = 0 x nd84) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved plm-v rdi code[2:0] transmit rdi-v upon plm-v r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 1 0 0
preliminary XRT86SH221 304 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit [7:5] - tim-v rdi code[2:0]: these three read/write bit-field permits the user t o specify the value that the vt-mapper block will t ransmit, within the rdi-v bit-fields of the k4 byte (within each ou tbound vt-frame) whenever (and for the duration tha t) the corresponding vt-de-mapper block detects and declar e the tim-v defect condition. n ote : in order to enable this feature, the user must set bit 4 (transmit rdi-v upon tim-v) within this regis ter to "1". bit 4 - transmit rdi-v upon tim-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the rdi code (as configured in bits 7 through 5 - within this re gister) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the t im-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the rdi code (via the k4 byte) whenev er (and for the duration that) the corresponding vt-de-mapper b lock declares the tim-v defect condition. 1 - configures the vt-mapper block to automatically transmit the rdi code (via the k4 byte) whenever ( and for the duration that) the corresponding vt-de-mapper block declares the tim-v defect condition. bit [3:1] - uneq-v rdi code[2:0]: these three read/write bit-field permits the user t o specify the value that the vt-mapper block will t ransmit, within the rdi-v bit-fields of the k4 byte (within each ou tbound vt-frame) whenever (and for the duration tha t) the corresponding vt-de-mapper block detects and declar e the uneq-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon uneq-v) within this regi ster to "1". bit 0 - transmit rdi-v upon uneq-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this re gister) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the u neq-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the rdi code (via the k4 byte) whenev er (and for the duration that) the corresponding vt-de-mapper b lock declares the uneq-v defect condition. 1 - configures the vt-mapper block to automatically transmit the rdi code (via the k4 byte) whenever ( and for the duration that) the corresponding vt-de-mapper block declares the uneq-v defect condition t able 269: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 2 (vtmrdicr2 = 0 x nd85) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-v rdi code[2:0] transmit rdi-v upon tim-v uneq-v rdi code[2:0] transmit rdi-v upon uneq-v r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 1 1 0 0
XRT86SH221 preliminary 305 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit [7:5] - lop-v rdi code[2:0]: these three read/write bit-field permits the user t o specify the value that the vt-mapper block will t ransmit, within the rdi-v bit-fields of the k4 byte (within each ou tbound vt-frame) whenever (and for the duration tha t) the corresponding vt-de-mapper block detects and declar e the lop-v defect condition. n ote : in order to enable this feature, the user must set bit 4 (transmit rdi-v upon lop-v) within this regis ter to "1". bit 4 - transmit rdi-v upon lop-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the rdi code (as configured in bits 7 through 5 - within this re gister) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the l op-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the rdi code (via the k4 byte) whenev er (and for the duration that) the corresponding vt-de-mapper b lock declares the lop-v defect condition. 1 - configures the vt-mapper block to automatically transmit the rdi code (via the k4 byte) whenever ( and for the duration that) the corresponding vt-de-mapper block declares the lop-v defect condition. bit [3:1] - ais-v rdi code[2:0]: these three read/write bit-field permits the user t o specify the value that the vt-mapper block will t ransmit, within the rdi-v bit-fields of the k4 byte (within each ou tbound vt-frame) whenever (and for the duration tha t) the corresponding vt-de-mapper block detects and declar e the ais-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon ais-v) within this regis ter to "1". bit 0 - transmit rdi-v upon ais-v: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this re gister) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the a is-v defect condition. 0 - configures the vt-mapper block to not automatic ally transmit the rdi code (via the k4 byte) whenev er (and for the duration that) the corresponding vt-de-mapper b lock declares the ais-v defect condition. 1 - configures the vt-mapper block to automatically transmit the rdi code (via the k4 byte) whenever ( and for the duration that) the corresponding vt-de-mapper block declares the ais-v defect condition t able 270: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 1 (vtmrdicr1 = 0 x nd86) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 lop-v rdi code[2:0] transmit rdi-v upon lop-v ais-v rdi code[2:0] transmit rdi-v upon ais-v r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
preliminary XRT86SH221 306 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu bit 7 - rfi-v upon e1 rai enable: this read/write bit-field permits the user to confi gure the vt-mapper block to automatically transmit the rfi-v indicator (within the outbound vt-data-stream) when ever (and for the duration) that the corresponding ingress direction receive e1 framer block declares the rai defect con dition. 0 - does not configure the vt-mapper block to autom atically transmit the rfi-v indicator whenever (and for the duration) that the corresponding ingress direction receive e1 framer block declares the rai defect con dition. 1 - configures the vt-mapper block to automatically transmit the rfi-v indicator whenever (and for the duration) that the corresponding ingress direction receive e1 fram er block declares the rai defect condition. bit 6 - reserved bit 5 - reserved: bit [4:2] - transmit rdi-v value[2:0]: these three read/write bit-fields permits the user to specify the value that the vt-mapper block will transmit, within the rdi-v bit-fields of the k4 byte (within each ou tbound vt-frame) regardless of any defects that the corresponding vt-de-mapper block is (or is not) currently declari ng. n ote : the user must set bit 0 (rdi-v insert type) within this register to "1" in order to configure the vt-m apper block to use these bit-fields as the "source" of the rdi- v value. bit 1 - rdi-v type: this read/write bit-field permits the user to confi gure the vt-mapper block to either support the "srd i-v" (single- bit - rdi-v) or "erdi-v" (extended - rdi-v) form of signaling. if the user opts to use only "single-b it" rdi-v, then the rdi-v indicator will only be transported via bit 0 (rdi-v) within the v5 byte in a vt-data-stream. co nversely, if the user opts to use the "extended" rdi-v, then the rdi-v in dicator will be transported via both bit 0 (rdi-v) within the v5 byte, and bits 3, 2 and 1 within the z7/k4 byte. 0 - configures the vt mapper block to use the srdi- v form of signaling. 1 - configures the vt-mapper block to use the erdi- v form of signaling. n ote : this configuration setting only applies to the vt-m apper block. if the user wishes to configure the v t-de- mappe block to support either the "srdi-v" or the " erdi-v" form of signaling, then he/she must set bit 0 (rdi- v type) within the "channel control - vt-de-mapper block - egress direction - e1 drop control register - byte 2. t able 271: c hannel c ontrol - vt-m apper t ransmit rdi-v c ontrol r egister 0 (vtmrdicr0 = 0 x nd87) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rfi-v upon e1 rai enable reserved reserved transmit rdi-v value[2:0] rdi-v type rdi-v insert type r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
XRT86SH221 preliminary 307 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 bit 0 - rdi-v insert type: this read/write bit-field permits the user to selec t the source of the rdi-v code word that the vt-map per block will transmit within the outbound vt-data-stream, as dep icted below. in this case, the user has two option s. ? to configure the vt-mapper block to transmit the ap propriate rdi-v code (based upon defects that the corresponding vt-de-mapper block declares). in thi s case, the vt-mapper block will transmit the rdi-v codes, as configured in the "channel control - vt mapper bloc k - ingress direction - transmit rdi-v control regi ster - bytes 3 - 1" registers. ? to configure the vt-mapper block to use the value w ritten into the "transmit rdi-v value[2:0]" bit-fie lds within this register. 0 - configures the vt-mapper block to transmit the appropriate rdi-v code (based upon defects that the corresponding vt-de-mapper block declares). 1 - configures the vt-mapper block to use the value written into the "transmit rdi-v value[2:0]" bit-f ields within this register. receive j2 trace identifier message - 16 byte messa ge buffer: address location: 0xne00 - 0xne0f receive j2 trace identifier message - 64 byte messa ge buffer: address location: 0xne00 - 0xne3f n ote : j2 trace identifier 64-byte messaging is not permit ted when n2 access point indentifier 16-byte messag ing is enabled. receive n2 access point identifier message - 16 byt e message buffer: address location: 0xne20 - 0xne2f n ote : j2 trace identifier 64-byte messaging is not permit ted when n2 access point indentifier 16-byte messag ing is enabled. t able 272: r eceive j2 t race i dentifier m essage m emory b uffer (vtdj2mem00 = 0 x ne00 - vtdj2mem3f = 0 x ne3f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 j2 trace identifier message byte[0:63] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 273: r eceive n2 a ccess p oint i dentifier m essage m emory b uffer (vtdn2mem20 = 0 x ne20 - vtdn2mem2f = 0 x ne2f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n2 access point identifier message byte[0:15] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH221 308 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu transmit j2 trace identifier message - 16 byte mess age buffer: address location: 0xnf00 - 0xnf0f transmit j2 trace identifier message - 64 byte mess age buffer: address location: 0xnf00 - 0xnf3f n ote : j2 trace identifier 64-byte messaging is not permit ted when n2 access point indentifier 16-byte messag ing is enabled. transmit n2 access point identifier message - 16 by te message buffer: address location: 0xnf20 - 0xnf2f n ote : j2 trace identifier 64-byte messaging is not permit ted when n2 access point indentifier 16-byte messag ing is enabled. t able 274: t ransmit j2 t race i dentifier m essage m emory b uffer (vtmj2mem00 = 0 x nf00 - vtmj2mem3f = 0 x nf3f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 j2 trace identifier message byte[0:63] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 275: t ransmit n2 a cess p oint i dentifier m essage m emory b uffer (vtmn2mem20 = 0 x nf20 - vtmn2mem2f = 0 x nf2f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n2 access point identifier message byte[0:15] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH221 preliminary 309 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 7.0 microprocessor interface timing 7.1 microprocessor interface timing - intel asynchro nous mode in intel asynchronous mode the active signals are a ddr[17:0], data[7:0], cs , ale, wr , rd and rdy . a read cycle starts with assertion of cs , address is assumed to be stable at this time sinc e cs is usually derived from the decoding the address bus. inside xrt86sh22 1 address is latched on the falling edge of the ale input. address may change on the addr inputs after the fal ling edge of the ale. multiplexed address & data bus is supported in this mode using ale input. it is possible to pull-up th e ale input if multiplexed address and data mode is not used. i n this case the address should be stable through en tire read or write instruction cycle. following falling edge of ale, rd is asserted for the read operation. rd must remain asserted until rdy is asserted by the XRT86SH221 device, which indicates data from the addressed location is available on th e data bus. rd and cs can be de-asserted when the data has been read by the processor. operation with wait-states is also possible, provid ed the wait is longer than the minimum cycle time. use of rdy is recommended for timing efficiency since the read cycle time can vary depending on the internal addr ess location being accessed. write operation is identical to read operation exce pt that following falling edge of ale wr is asserted. data to be written at the addressed location should be v alid on the data bus at the time wr is asserted. wr should remain asserted until rdy is asserted by the XRT86SH221 device. following rd y assertion wr and cs may be de-asserted. note: the values for t0 through t10, within this fig ure can be found in table 276 . f igure 55. i ntel -a synchronous m ode t iming - w rite o peration ale/as a[17:0] cs d[7:0] wr/r/w data to be written address of target register rd/ds rdy/dtack t0 t1 t2 t3 t4 t5 t10
preliminary XRT86SH221 310 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu note: the values for t0 through t10, in this figure can be found in table 277 . table 276 intel asynchronous mode timing - write oper ation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timingsymbol description min. typ. max. units t0 address setup time to ale "low" 5 - - ns t1 address hold time from ale "low" 5 - - ns t2 wr strobe pulse width 150 - - ns t3 data setup time to wr "low" 25 - - ns t4 data hold time from wr "low" 200 - - ns t5 ale "low" set-up time to wr "low" 50 - - ns t10 wr "low" to rdy "low" delay time - - 125 ns f igure 56. i ntel -a synchronous m ode t iming - r ead o peration table 277 intel asynchronous mode timing - read opera tion test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timingsymbol description min. typ. max. units t0 address setup time to ale "low" 5 - - ns t1 address hold time from ale "low" 5 - - ns t2 rd strobe pulse width 200 - - ns t5 ale "low" set-up time to rd "low" 50 - - ns t6 data invalid delay from rd high - - 9 ns rd/ds rdy/dtack ale/as a[17:0] cs d[7:0] not valid valid address of target register wr/r/w t0 t1 t2 t5 t12 t6
XRT86SH221 preliminary 311 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 7.2 microprocessor interface timing - motorola async hronous (68k) mode in motorola asynchronous mode the active signals ar e addr[17:0], data[7:0], cs , rw , ds and dtack . a read cycle starts with rw being 'high' and assertion of cs , address is assumed to be stable at this time sinc e cs is usually derived from the decoding the address b us. in this mode the address should be stable through e ntire read or write instruction cycle. following falling edge of cs , ds is asserted for the read operation. ds must remain asserted until dtack is asserted by the XRT86SH221 device, which indicates data from the addressed location is available on th e data bus. ds and cs can be de-asserted when the data has been read by the processor. operation with wait-states is also possible, provid ed the wait is longer than the minimum cycle time. use of dtack is recommended for timing efficiency since the rea d cycle time can vary depending on the internal address location being accessed. write operation is identical to read operation exce pt that the cycle starts with rw being 'low', followed by cs assertion further followed by assertion of ds . data to be written at the addressed location shou ld be valid on the data bus at the time ds is asserted. ds should remain asserted until dtack is asserted by the XRT86SH221 device. following assertion of dtack ds and cs may be de-asserted. note: the values for t15 through t22 can be found in table 278 . t12 rd low to rdy low delay time - - 125 ns f igure 57. m otorola -a synchronous m ode t iming - w rite o peration table 278 motorola (68k) asynchronous mode timing inf ormation - write operation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timing description min. typ. max units t15 data setup time to ds "low" 25 - - ns t16 data hold time to ds "low" 150 - - ns t17 ds "high" to dtack "high" - - 9 ns t21 cs "low" to ds set-up time 50 - - ns table 277 intel asynchronous mode timing - read opera tion a[17:0] cs d[7:0] rd/ds rdy/dtack data to be written address of target register wr/r/w t15 t16 t17 t21 t22
preliminary XRT86SH221 312 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu note: the values for t13 through t24 can be found in table 278 . t22 ds "low" to dtack "low" delay time 130 - - ns 7.2.1 motorola-asynchronous mode timing - read oper ation f igure 58. m otorola -a synchronous m ode t iming - r ead o peration table 279 motorola (68k) asynchronous mode timing - r ead operation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timing description min. typ. max units t19 ds "high" to dtack "high" - - 8 ns t20 dtack "high" to data invalid - - 8 ns t21 cs "low" to ds set-up time 50 - - ns t22 ds "low" to dtack "low" delay time 120 - - ns table 278 motorola (68k) asynchronous mode timing inf ormation - write operation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timing description min. typ. max units rd/ds a[17:0] cs d[7:0] rdy/dtack not valid valid data address of target register wr/r/w t19 t20 t21 t22
XRT86SH221 preliminary 313 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 7.3 powerpc 403 synchronous mode: in powerpc mode the active signals are addr[17:0], data[7:0], cs , rw , we , dben , rdy and pclk. in this mode all input signals are sampled by the pclk. for all inputs minimum setup time is 4ns and minimum h old time is 3ns. maximum pclk frequency is 66 mhz. a read cycle starts with rw being 'high' and assertion of cs , address is assumed to be stable at this time since cs is usually derived from the decoding the address b us. following falling edge of cs , dben is asserted for the read operation. dben must remain asserted until rdy is asserted by the XRT86SH221 device, which indicat es data from the addressed location is available on the data bus. dben and cs can be de-asserted when the data has been read by the processor. we should be high during the entire read cycle. operation with wait-states is also possible, provid ed the wait is longer than the minimum cycle time. use of rdy is recommended for timing efficiency since the read cycle time can vary depending on the internal addr ess location being accessed. write operation is identical to read operation exce pt that the cycle starts with rw being 'low', followed by cs assertion further followed by assertion of we . data to be written at the addressed location shou ld be valid on the data bus at the time we is asserted. we should remain asserted until rdy is asserted by th e XRT86SH221 device. following rdy assertion we and cs may be de-asserted. dben should be high during the entire write cycle. note: the value for t25 through t38 can be found in table 280 . f igure 59. p ower pc 403 m ode t iming - w rite o peration table 280 power pc403 mode timing - write operation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timing description min. typ. max. units t23 r/w "low" to rising edge of pclk set-up time (write operation) 5 - - ns t24 cs "low" to rising edge of pclk set-up time 5 - - ns t25 rising edge of pclk to rdy "low" delay 4 - - ns 1 10 9 8 7 6 5 4 3 2 pclk r/w we d[7:0] rdy 8 pclk cycles note: pclk = 33mhz a[17:0] cs after 1 pclk cycle of cs going "low" t23 t24 t25
preliminary XRT86SH221 314 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu note: the value for t25 through t38 can be found in table 281 . f igure 60. p ower pc 403 m ode t iming - r ead o peration table 281 power pc403 mode timing - read operation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timing description min. typ. max. units t24 cs "low" to rising edge of pclk set-up time 5 - - ns t25 rising edge of pclk to rdy low delay 4 - - ns t27 r/w high to rising edge of pclk set-up time 5 - - ns 1 10 9 8 7 6 5 4 3 2 pclk d[7:0] rdy a[17:0] cs we r/w 8 pclk cycles not valid valid 7 pclk cycles t25 t24 t27
XRT86SH221 preliminary 315 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 7.4 microprocessor interface timing - mcp860 synchro nous mode in mpc86x mode the active signals are addr[17:0], d ata[7:0], cs , rw , we , dben , ta and pclk. in this mode all input signals are sampled by the pclk. for all inputs minimum setup time is 4ns and minimum h old time is 3ns. maximum pclk frequency is 66 mhz. a read cycle starts with rw being 'high' and assertion of cs , address is assumed to be stable at this time since cs is usually derived from the decoding the address b us. following falling edge of cs , dben is asserted for the read operation. dben must remain asserted until ta is asserted by the XRT86SH221 device, which indicat es data from the addressed location is available on the data bus. dben and cs can be de-asserted when the data has been read by the processor. we should be high during the entire read cycle. operation with wait-states is also possible, provid ed the wait is longer than the minimum cycle time. use of ta is recommended for timing efficiency since the read cycle time can vary depending on the internal addr ess location being accessed. write operation is identical to read operation exce pt that the cycle starts with rw being 'low', followed by cs assertion further followed by assertion of we . data to be written at the addressed location shou ld be valid on the data bus at the time we is asserted. we should remain asserted until ta is asserted by the XRT86SH221 device. following assertion of ta we and cs may be de-asserted. dben should be high during the entire write cycle. f igure 61. mpc86x m ode t iming - w rite o peration table 282 mpc86x mode timing - write operation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timing description min. typ. max. units t23 r/w "low" to rising edge of pclk set-up time (write operation) 5 - - ns t24 cs "low" to rising edge of pclk set-up time 4 - - ns t25 rising edge of pclk to rdy highdelay 4 - - ns 1 10 9 8 7 6 5 4 3 2 pclk r/w we d[7:0] rdy 8 pclk cycles note: pclk = 33mhz a[17:0] cs after 1 pclk cycle t23 t24 t25
preliminary XRT86SH221 316 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu f igure 62. mpc86x m ode t iming - r ead o peration table 283 mpc86x timing information - read operation test conditions: ta = 25c, vcc = 3.3v5% and 1.8v 5%, unless otherwise specified timing description min. typ. max. units t24 cs "low" to rising edge of pclk set-up time 5 - - ns t25 rising edge of pclk to rdy high delay 4 - - ns t27 r/w high to rising edge of pclk set-up time 5 - - ns 1 10 9 8 7 6 5 4 3 2 pclk d[7:0] rdy a[17:0] cs we r/w 8 pclk cycles not valid valid 7 pclk cycles t25 t24 t27
XRT86SH221 preliminary 317 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 8.0 interface timing specifications 8.1 stm-0/stm-1 telecom bus interface timing informa tion this section presents the timing requirements of th e stm-0/stm-1 telecom bus interface, for the follow ing conditions/modes. ? whenever the stm-0/stm-1 telecom bus interface has been configured to operate in the stm-0 mode. ? whenever the stm-0/stm-1 telecom bus interface has been configured to operate in the stm-1 slot maste r mode ? whenever the stm-0/stm-1 telecom bus interface has been configured to operate in the stm-1 slot slave mode this section presents the timing requirements for t he stm-0/stm-1 telecom bus interface. in particula r this section indicates the following. a) identifies which edge of txa_clk in which the txa _d[7:0], txa_pl, txa_c1j1v1_fp, txa_alarm and txa_dp output pins are updated on. b) the clock to output delays (from the rising edge of txa_clk to the instant that the txa_d[7:0], txa_ pl, txa_c1j1v1_fp, txa_alarm and txa_dp output pins are updated. c) identifies which edge of rxd_clk that the rxd_d[7 :0], rxd_pl, rxd_c1j1v1_fp, rxd_alarm and rxd_dp input pins are sampled on. d) the set-up time requirements (from an update in t he rxd_d[7:0], rxd_pl, rxd_c1j1v1_fp, rxd_alarm and rxd_dp input signals to the rising ed ge of rxd_clk). e) the hold-time requirements (from the rising edge of rxd_clk to a change in the rxd_d[7:0], rxd_pl, rxd_c1j1v1_fp, rxd_alarm and rxd_dp input signals) 8.2 the transmit stm-0/stm-1 telecom bus interface t iming - stm-0 applications whenever the transmit stm-0/stm-1 telecom bus inter face has been configured to operate in the stm-0 mode, then all of the signals (which are output via this bus interface) are updated upon the falling e dge of txa_clk (6.48mhz clock signal). note: the value for t51 can be found in table 284 . f igure 63. a n i llustration of the w aveforms of the s ignals that are output via the t ransmit stm-0/ stm-1 t elecom b us i nterface ( for stm-0 a pplications ) t51 txa_clk txa_d[7:0] txa_pl txa_c1j1v1_fp a2 c1 c1 j1 dat a j1
preliminary XRT86SH221 318 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.3 the transmit stm-0/stm-1 telecom bus interface t iming - stm-1 slot master applications whenever the transmit stm-0/stm-1 telecom bus inter face has been configured to operate in both the stm - 1 and the slot master mode, then all of the signals (which are output via this bus interface) are upda ted upon the falling edge of txa_clk (19.44mhz clock signal) . if the XRT86SH221 is configured to operate as the s lot master, then it will pulse the txsbfp_in_out ou tput pin "high" coincident to the instant that the chip outputs the very first byte of a given stm-1 frame. the XRT86SH221 will update the txsbfp_in_out output pin upon the falling edge of txa_clk. table 284 timing information for the transmit stm-0 t elecom bus interface - stm-0 applications symbol description min. typ. max. t51 falling edge of txa_clk to updates in txa_d[7:0], t xa_pl, txa_c1j1v1_fp and txa_dp 2.0ns 3.1ns f igure 64. a n i llustration of the w aveforms of the s ignals that are output via the t ransmit stm-0/ stm-1 t elecom b us i nterface ( for stm-1 a pplications ) t52 txa_clk txa_d[7:0] txa_pl txa_c1j1v1_fp a2 c1 c1 j1 data j1
XRT86SH221 preliminary 319 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 f igure 65. a n i llustration of the timing relationships between the t x sbfp_in_out output pin , and the t x a_clk output pin , within the t ransmit stm-1 t elecom b us i nterface (s lot m aster m ode a ppli - cation ) table 285 timing information for the transmit stm-0/s tm-1 telecom bus interface - stm-1 slot master applications symbol description min. typ. max. t52 falling edge of txa_clk to updates in txa_d[7:0], t xa_pl, txa_c1j1v1_fp and txa_dp 2.0ns 4.0ns t53 falling edge of txa_clk to update in the txsbfp_in_ out signal 0.1 0.3 txa_d[7:0] txsbfp_in_out data a1 a1 data data data txa_clk t53 tx_51_19mhz
preliminary XRT86SH221 320 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.4 the transmit stm-0/stm-1 telecom bus interface t iming - stm-1 slot slave applications whenever the transmit stm-0/stm-1 telecom bus inter face has been configured to operate in the stm-1, then all of the signals (which are output via this bus interface) are updated upon the falling edge of txa_clk (19.44mhz clock signal). if the XRT86SH221 is configured to operate as the s lot slave, then it will sample the txsbfp_in_out si gnal via an internal clock. the timing relationship bet ween the txsbfp_in_out signal and the other transmi t stm- 0/stm-1 telecom bus interface signals is presented below in figure 67 . f igure 66. a n i llustration of the w aveforms of the s ignals that are output via the t ransmit stm-0/ stm-1 t elecom b us i nterface ( for stm-1 a pplications ) f igure 67. a n i llustration of the timing relationships between the t x sbfp input pin and the t x a_clk output pin within the t ransmit stm-0/stm-1 t elecom b us i nterface (stm-1 s lot s lave a pplications ) t54 txa_clk txa_d[7:0] txa_pl txa_c1j1v1_fp a2 c1 c1 j1 data j1 txa_d[7:0] txsbfp_in_out data a1 a1 data data data txa_clk tx_51_19mhz t57 t58
XRT86SH221 preliminary 321 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 note: in slave mode, txsbfp_in_out is input to xrt86 sh221. inputs are applied using input clock tx_51_1 9mhz and are sampled on rising edge of tx_51_19mhz internall y. the t57 parameter is referenced to the rising ed ge of tx_51_19mhz, which provides the minimum setup and h old time required for txsbfp_in_out. txa_clk should be used to sampe the output signals not the input sign als. 8.5 the receive stm-0/stm-1 telecom bus interface ti ming - stm-0 applications whenever the receive stm-0/stm-1 telecom bus interf ace has been configured to operate in the stm-0 mode, then all of the signals (which are accepted v ia this bus interface) are sampled upon the rising edge of rxd_clk (6.48mhz clock signal). note: the value for t59 and t60 can be found in table 287 . the data and control signals are applied on the f alling edge of rxd_clk. the XRT86SH221 samples the data and contro l signals on the rising edge of rxd_clk. table 286 timing information for the transmit stm-0/stm-1 te lecom bus interface - stm-1 slot slave applications symbol description min. typ. max. t54 falling edge of txa_clk to updates in txa_d[7:0], t xa_pl, txa_c1j1v1_fp and txa_dp 1.1ns 2.5ns t57 txsbfp set-up time to rising edge of tx51_19mhz 6ns t58 rising edge of tx51_19mhz to txsbfp_in_out hold tim e 1ns f igure 68. a n i llustration of the w aveforms of the s ignals that are i nput via the r eceive stm-0/ stm-1 t elecom b us i nterface table 287 timing information for the receive stm-0/stm-1 telecom bu s interface - stm-0 applications symbol description min. typ. max. t59 rxd_d[7:0], rxd_pl, rxd_c1j1v1_fp, rxd_alarm and rxd_dp to rising edge of rxd_clk set-up time requir ements 6 ns t60 rxd_clk rxd_d[7:0] rxd_pl rxd_c1j1v1_fp a2 c1 c1 j1 data data t59
preliminary XRT86SH221 322 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.6 the receive stm-0/stm-1 telecom bus interface ti ming - stm-1 applications whenever the receive stm-0/stm-1 telecom bus interf ace has been configured to operate in the stm-1 mode, then all of the signals (which are accepted v ia this bus interface) are sampled upon the rising edge of rxd_clk (19.44mhz clock signal). note: the value for t61 and t62 can be found in table 288 . t60 rising edge of rxd_clk to rxd_d[7:0], rxd_pl, rxd_c1j1v1_fp, rxd_alarm and rxd_dp hold time requirements 2 ns f igure 69. a n i llustration of the w aveforms of the s ignals that are i nput via the r eceive stm-0/ stm-1 t elecom b us i nterface table 288 timing information for the receive stm-0/stm-1 telecom bu s interface - stm-1 applications symbol description min. typ. max. t61 rxd_d[7:0], rxd_pl, rxd_c1j1v1_fp, rxd_alarm and rxd_dp to rising edge of rxd_clk set-up time requir ements 6 ns t62 rising edge of rxd_clk to rxd_d[7:0], rxd_pl, rxd_c1j1v1_fp, rxd_alarm and rxd_dp hold time requirements 2 ns table 287 timing information for the receive stm-0/stm-1 telecom bu s interface - stm-0 applications symbol description min. typ. max. rxd_clk rxd_d[7:0] rxd_pl rxd_c1j1v1_fp a2 c1 c1 j1 data data t61 t62
XRT86SH221 preliminary 323 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 8.7 stm-0 liu interface timing information in addition to the telecom bus, the XRT86SH221 can be configured for high-speed stm-0/stm-1 liu interface ports. 8.7.1 receive stm-0/stm-1 liu interface timing note: the values for t63 and t64 are presented in table 289 . f igure 70. a n i llustration of the w aveforms of the r eceive stm-0/stm-1 signals that are input to the r eceive stm-0/stm-1 liu i nterface b lock - s hared p ort table 289 timing information for the receive stm-0/stm-1 liu interfa ce when the receive stm-0/ stm-1 toh processor block has been configured to sam ple the rxstm0data signal upon the rising edge of the rxstm0clk signal symbol description min. typ. max. t63 rxstm0data to rising edge of rxstm0clk set-up time requirements 5ns t64 rising edge of rxstm0clk to rxstm0data hold time requirements 0ns rxstm0data rxstm0clk t63 t64
preliminary XRT86SH221 324 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.7.2 transmit stm-0/stm-1 liu interface timing note: the value for t65 is presented in table 290 . f igure 71. a n i llustration of the w aveforms of the stm-0/stm-1 signals that are output from the t ransmit stm-0/stm-1 liu i nterface - d edicated p ort table 290 timing information for the transmit stm-0/stm-1 liu interf ace when the transmit stm-0/ stm-1 toh processor block has been configured to upda te the txstm0data signal upon the rising edge of the txstm0clk signal symbol description min. typ. max. t65 rising edge of txstm0clk to txstm0data output delay 2.0ns 5.0ns txstm0data txstm0clk t65
XRT86SH221 preliminary 325 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 8.8 transmit stm-0/stm-1 toh and poh data input port the transmit stm-0/stm-1 toh and poh data input por t is used to insert a value for the toh and poh byt es into the outbound stm-0/stm-1 data-stream. note: the txohins and the txoh input pins are sample d (by the transmit stm-0/stm-1 toh and poh overhead input port) upon the rising edge of txohclk. all of the remaining signals (e.g., txohframe and txohenable) are updated upon the falling edge of txohclk. note: the values for t65, t66 and t67 can be found i n table 291 . note: the XRT86SH221 uses faster sysclk (49mhz) and enable at stm-0 byte rate (6.48mhz) to generate all the outputs including txohclk, txohenable and txohframe. this c an make t65 have negative min and max times.the ris ing of txohclk should be used to sample txohenable and txohframe which provides enough setup and hold time s. f igure 72. i llustration of t iming w ave - form of the t ransmit stm-0/stm-1 toh and poh o verhead d ata i nput p ort table 291 timing information for the transmit stm-0/stm-1 toh and p oh overhead data input port symbol description min. typ. max. t65 falling edge of txohclk to rising edge of txohframe , txohenable and txpohind output delay -3.0ns -2.0ns t66 txohins to rising edge of txohclk set-up time 6.0ns t67 txoh data to rising edge of txohclk set-up time 6.0ns f1 txohclk frequency 3.08mh z txoh txohins txohclk txohframe txohenable t65 t66 t67
preliminary XRT86SH221 326 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.9 transmit vc-4 poh data input port the transmit vc-4 poh data input port is used to in sert a value for the vc-4 poh bytes into either the outbound vc-4 data-stream (which is output via the transmit stm-1 telecom bus. note: the txtupohins and the txtupoh input pins are sampled (by the transmit vc-4 poh data input port) upon the rising edge of txtupohclk. all of the remaining si gnals (e.g., txtupohframe and txtupohenable) are up dated upon the falling edge of txtupohclk. note: the values for t68, t69 and t70 can be found i n table 292 . f igure 73. i llustration of t iming w ave - form of the t ransmit vc-4 poh d ata i nput p ort table 292 timing information for the transmit vc-4 poh data input po rt symbol description min. typ. max. t68 falling edge of txtupohclk to rising edge of txtupo hframe and txtupohvalid output delay -0.5ns 0.5ns t69 txtupohins to rising edge of txtupohclk set-up time 6ns t70 txtupoh data to rising edge of txtupohclk set-up ti me 6ns txtupoh txtupohins txtupohclk txtupohframe txtupohenable t68 t69 t70
XRT86SH221 preliminary 327 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 8.10 receive stm-0/stm-1 toh and poh data output por t the receive stm-0/stm-1 toh and poh data output por t is used to extract out the values of the toh and poh bytes within the incoming stm-0/stm-1 data-stre am. all of the receive toh and poh data output por t signals are updated upon the falling edge of rxohcl k. note: the values for t71 and t72 can be found in table 293 . f igure 74. i llustration of the t iming w ave - form of the r eceive stm-0/stm-1 toh and poh d ata o ut - put p ort table 293 timing information for the receive stm-0/stm-1 toh and po h data output port symbol description min. typ. max. t71 falling edge of rxohclk to rising edge of rxohframe , rxohvalid, and rxpohind -0.2ns 0.2ns t72 falling edge of rxohclk to rxoh output delay -0.2ns 0.2ns rxoh rxohclk rxohframe rxohvalid t71 t72
preliminary XRT86SH221 328 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.11 receive vc-4 poh data output port the receive vc-4 poh overhead output port is used t o extract out the values of the vc-4 poh bytes with in the incoming stm-1 data-stream. all of the receive vc-4 poh overhead output port signals are updated upon the falling edge of rxtupohclk. the timing wave-fo rm and information for the receive vc-4 poh data ou tput port is presented below. note: the values for t73 and t74 can be found in table 294 . f igure 75. i llustration of the t iming w ave - form of the r eceive vc-4 poh d ata o utput p ort table 294 timing information for the receive vc-4 poh data output p ort symbol description min. typ. max. t73 falling edge of rxtupohclk to rising edge of rxtupo hframe and rxtupohvalid -0.2ns 0.2ns t74 falling edge of rxtupohclk to rxtupoh output delay -0.2ns 0.2ns rxtupoh rxtupohclk rxtupohframe rxtupohvalid t73 t74
XRT86SH221 preliminary 329 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 8.12 ingress direction - add/drop port timing 8.12.1 ingress direction - add port timing f igure 76. i llustration of the i ngress -d irection a dd p ort s ignals table 295 timing information for the ingress-direction add port sig nals timing symbol description min typ max units t79 ig_te1txdata[7:0] to rising edge of ig_te1txclk set -up time 4.5 ns t80 rising edge of ig_te1txclk to ig_te1txdata[7:0] hol d time 3.0 ns t81 ig_te1txohind[4:0] to rising edge of ig_te1txclk se t up time 4.5 ns t82 rising edge of ig_te1txclk to ig_te1txohind[4:0] ho ld time 3.0 ns t83 ig_te1txslot0 to rising edge of ig_te1txclk set-up time 5.0 ns t84 rising edge of ig_te1txclk to ig_te1txslot0 hold ti me 3.0 ns t85 ig_te1txvalid to rising edge of ig_te1txclk set-up time 5.0 ns t86 rising edge of ig_te1txclk to ig_te1txvalid hold ti me 3.0 ns ig_te1txdata[7:0] ig_te1txvalid ig_te1txclk ig_te1txslot0 ig_te1txohind[4:0] t79 t80 t81 t82 t83 t84 t85 t86
preliminary XRT86SH221 330 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.12.2 ingress direction - drop port timing f igure 77. i llustration of the i ngress -d irection d rop p ort s ignals table 296 timing information for the ingress-direction drop port s ignals timing symbol description min typ max units t87 falling edge of ig_te1rxclk to ig_te1rxvalid output delay -0.2 3.0 ns t88 rising edge of ig_te1rxclk to ig_te1rxdata[7:0] hol d time 6.0 ns t89 ig_te1rxohind[4:0] to rising edge of ig_te1rxclk se t up time 4.5 ns t90 rising edge of ig_te1rxclk to ig_te1rxohind[4:0] ho ld time 6.0 ns ig_te1rxdata[7:0] ig_te1rxvalid ig_te1rxclk ig_te1rxslot0 ig_te1rxohind[4:0] t88 t87 t89 t90
XRT86SH221 preliminary 331 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 8.13 egress direction - add/drop port timing 8.13.1 egress direction - add port timing f igure 78. i llustration of the e gress -d irection a dd p ort s ignals table 297 timing information for the egress-direction add port s ignals timing symbol description min typ max units t91 eg_te1txdata[7:0] to rising edge of eg_te1txclk set -up time 7.0 ns t92 rising edge of eg_te1txclk to eg_te1txdata[7:0] hol d time 2.0 ns t93 eg_te1txohind[4:0] to rising edge of eg_te1txclk se t up time 7.0 ns t94 rising edge of eg_te1txclk to eg_te1txohind[4:0] ho ld time 2.0 ns t95 eg_te1txslot0 to rising edge of eg_te1txclk set-up time 7.0 ns t96 rising edge of eg_te1txclk to eg_te1txslot0 hold ti me 2.0 ns t97 eg_te1txvalid to rising edge of eg_te1txclk set-up time 7.0 ns t98 rising edge of eg_te1txclk to eg_te1txvalid hold ti me 2.0 ns eg_te1txdata[7:0] eg_te1txvalid eg_te1txclk eg_te1txslot0 eg_te1txohind[4:0] t91 t92 t93 t94 t95 t96 t97 t98
preliminary XRT86SH221 332 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 8.13.2 egress direction - drop port timing f igure 79. i llustration of the e gress -d irection d rop p ort s ignals table 298 timing information for the egress-direction drop port s ignals timing symbol description min typ max units t99 falling edge of eg_te1rxclk to eg_te1rxvalid output delay -0.2 3.0 ns t100 rising edge of eg_te1rxclk to eg_te1rxdata[7:0] hol d time 6.0 ns t101 eg_te1rxohind[4:0] to rising edge of eg_te1rxclk se t up time 4.5 ns t102 rising edge of eg_te1rxclk to eg_te1rxohind[4:0] ho ld time 6.0 ns ig_te1rxdata[7:0] ig_te1rxvalid ig_te1rxclk ig_te1rxslot0 ig_te1rxohind[4:0] t100 t99 t101 t102
XRT86SH221 preliminary 333 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 9.0 electrical characteristics notes: 1. exposure to or operating near the min or max valu es for extended periods may cause permanent failure and impair reliabilty of the device. 2. esd testing method is per jesd22-a114. n ote : input leakage current excludes pins that are intern ally pulled "low" or "high" table 299 absolute maximum ratings symbol parameter min max units comments v dd supply voltage -0.5 3.465 v note 1 v dd18 supply voltage -0.5 1.890 v note 1 s temp storage temperature -65 +150 c note 1 a temp ambient operating temperature -40 +85 c linear air flo w (tbd) ft/min thetaja thermal resistance tbd c/w thetajc thermal resistance tbd c/w m levl exposure to moisture 5 level eia/jedec jesd22-a112-8 esd esd rating - hbm 2000 v note 2 vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =25c, unless otherwise specified p arameter s ymbol m in t yp m ax u nits power supply voltage (3.3v) vdd33 3.13 3.3 3.46 v power supply voltage (1.8v) vdd18 1.71 1.8 1.89 v current consumption (3.3v) 659 ma) current consumption (1.8v) 309 ma power consumption (3.3v) 2.175 w power consumption (1.8v) 556 mw total power consumption 2.73 w input high voltage v ih 2.0 - 5.0 v input low voltage v il -0.5 - 0.8 v output high voltage ioh=-2.0ma v oh 2.4 - v output low voltage iol=2.0ma v ol - - 0.4 v input leakage current i l - - 10 a input capacitance c i - 5.0 pf output load capacitance c l - - 25 pf
preliminary XRT86SH221 334 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu t able 300: e1 r eceiver e lectrical c haracteristics p arameter m in t yp . m ax u nit t est c onditions vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =25c, unless otherwise specified receiver loss of signal: number of consecutive zeros before los is set - 32 - bit cable attenuation @1024khz itu-g.775, ets1 300 233 input signal level at los 13 16 - db rlos clear 12.5 - - % ones receiver sensitivity cable + flat loss 6+6 - - db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w application. interference margin -18 -14 - db with 6db cable loss input impedance 15 - k w jitter tolerance: 1 hz 10khz---100khz 37 0.3 -- -- uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude - 20 36 0.5 khz db itu g.736 jitter attenuator corner frequency(-3db curve) jabw=0 jsbw=1 -- 10 1.5 -- hz hz itu g.736 return loss: 51khz --- 102khz 102khz --- 2048khz 2048khz --- 3072khz 12 18 14 -- - -- - db db db itu g.703
XRT86SH221 preliminary 335 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =25c, unless otherwise specified p arameter m in t yp m ax u nit t est c ondition ami output pulse amplitude 75 w 120 w 2.13 2.70 2.37 3.00 2.60 3.30 vv 1:2 transformer output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 itu-g.703 output pulse amplitude ratio 0.95 - 1.05 itu-g.703 jitter added by the transmitter output - 0.025 0.05 ui p-p broad band with jitter free tclk applied to the input. output return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 15 98 -- - -- - db db db etsi 300 166
preliminary XRT86SH221 336 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 10.0 background and protocols this section intends to provide a background covera ge of the theory of communication protocols involve d in voyager-lite development. only brief descriptions o f their formats, control flows, and application-spe cific features are presented here. 10.1 synchronous digtial hierarchy (sdh) standard this section intends to provide a background covera ge of the theory of communication protocols involve d in sdh standard. only brief descriptions of their rat es, formats, control flows, and application-specifi c features are presented here. synchronous digital hierarchy (sdh): the sdh is a hierarchical set of digital transport structures, standardized for the transport of suitably adapted payloads over physical transmission networks. synchronous transport module (stm): an stm is the information structure used to suppor t section layer connections in the sdh. it consists of information payload and section overhead (soh) information fiel ds organized in a block frame structure which repeats every 125 s. the information is suitably condition ed for serial transmission on the selected media at a rate which is synchronized to the network. a basic stm is defined at 155 520 kbit/s. this is termed stm-1. hi gher capacity stms are formed at rates equivalent t o n times this basic rate. stm capacities for n=4, n=16 , n=64 and n=256 are defined; higher values are und er consideration. the stm-0 comprises a single administrative unit of level 3. the stm-n, n = 1, comprises a single administrative unit group of level n (aug-n) togeth er with the soh. virtual container-n (vc-n): a virtual container is the information structure u sed to support path layer connections in the sdh. it consists of information payload and path overhead (poh) information fields organized in a block frame structure which repeats every 125 or 500 us. alignment information to ident ify vc-n frame start is provided by the server network layer . two types of virtual containers have been identifie d. lower order virtual container-n: vc-n (n=1, 2, 3). this element comprises a single container-n (n=1, 2, 3) plus the lower order virtual container poh appropriate to that level. higher order virtual container-n: vc-n (n=3, 4). th is element comprises either a single container-n (n=3, 4) or an assembly of tributary un it groups (tug-2s or tug-3s), together with virtual container poh appropriate to that level. administrative unit-n (au-n): an administrative unit is the information structur e which provides adaptation between the higher order path layer and the multipl ex section layer. it consists of an information pay load (the higher order virtual container) and an administrati ve unit pointer which indicates the offset of the p ayload frame start relative to the multiplex section frame start. two administrative units are defined. the au-4 cons ists of a vc-4 plus an administrative unit pointer which indicates the phase alignment of the vc-4 with resp ect to the stm-n frame. the au-3 consists of a vc-3 plus an administrative unit pointer which indicates the phase alignment of the vc-3 with respect to the st m-n frame. in each case the administrative unit pointer location is fixed with respect to the stm-n frame. one or more administrative units occupying fixed, d efined positions in an stm payload are termed an administrative unit group (aug). an aug-1 consis ts of a homogeneous assembly of au-3s or an au-4. tributary unit-n (tu-n): a tributary unit is an information structure which provides adaptation between the lower order path layer and the higher order path la yer. it consists of an information payload (the low er order virtual container) and a tributary unit pointer whi ch indicates the offset of the payload frame start relative to the higher order virtual container frame start. the tu-n (n=1, 2, 3) consists of a vc-n together wi th a tributary unit pointer. one or more tributary units, occupying fixed, defined positions in a higher orde r vc-n payload is termed a tributary unit group (tu g). tugs are defined in such a way that mixed capacity payloads made up of different size tributary units can be
XRT86SH221 preliminary 337 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 constructed to increase flexibility of the transpor t network. a tug-2 consists of a homogeneous assem bly of identical tu-1s or a tu-2. a tug-3 consists of a ho mogeneous assembly of tug-2s or a tu-3. container-n (n=1-4): a container is the information structure which for ms the network synchronous information payload for a virtual container. for ea ch of the defined virtual containers there is a cor responding container. adaptation functions have been defined f or many common network rates into a limited number of standard containers.
preliminary XRT86SH221 338 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 10.2 basic frame structure stm-n frame structure is shown in figure 80 . the three main areas of the stm-n frame are indic ated: soh; administrative unit pointer(s); information payload. f igure 80. stm-n frame structure stn-n payload administrative unit pointer(s) section overhead soh 9 rows section overhead soh 9 x n (3 for stm-0) 261 x n (87 for stm-0) 270 x n columns (bytes) (90 columns for stm-0) 13 4 5 9
XRT86SH221 preliminary 339 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 section overhead rows 1-3 and 5-9 of columns 1 to 9 x n of the stm-n in figure 80 are dedicated to the soh. administrative unit pointers row 4 of columns 1 to 9 n in figure 80 is available for administrative unit pointers. administrative units in the stm-n the stm-n payload supports one aug-n where the: a. aug-256 may consist of: 1. four aug-64; 2. one au-4-256c. b. aug-64 may consist of: 1. four aug-16; 2. one au-4-64c. c. aug-16 may consist of: 1. four aug-4; 2. one au-4-16c. d. aug-4 may consist of: 1. four aug-1; 2. one au-4-4c. e. aug-1 may consist of: 1. one au-4; 2. three au-3s. the vc-n associated with each au-n does not have a fixed phase with respect to the stm-n frame. the location of the first byte of the vc-n is indicated by the au-n pointer. the au-n pointer is in a fixe d location in the stm-n frame. the au-4 may be used to carry, via the vc-4, a numb er of tu-ns (n=1, 2, 3) forming a two-stage multipl ex. the vc-n associated with each tu-n does not have a fixe d phase relationship with respect to the start of t he vc-4. the tu-n pointer is in a fixed location in the vc-4 and the location of the first byte of the vc-n is indicated by the tu-n pointer. the au-3 may be used to carry, via the vc-3, a numb er of tu-ns (n=1, 2) forming a two-stage multiplex. the vc-n associated with each tu-n does not have a fixe d phase relationship with respect to the start of t he vc-3. the tu-n pointer is in a fixed location in the vc-3 and the location of the first byte of the vc-n is indicated by the tu-n pointer.
preliminary XRT86SH221 340 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu 11.0 reference documentation telcordia, transport systems generic requirements ( tsgr): common requirements gr-499-core issue 2, december 1998 itu-t recommendation g.707 network node interface f or the synchronous digital hierarchy (sdh) (03/96) itu-t recommendation g.783 characteristics of synch ronous digital hierarchy (sdh) equipment functional blocks (01/94) itu/ccitt recommendation o.151 error performance me asuring equipment operating at the primary rate and above (10/92) ansi t1.107, "digital hierarchy - formats specifica tions", 1988. ansi 1.107a, addendum to ansi t1.107, 1988", 1990. ansi t1.403 - 1999, network-to-customer installatio n - ds1 metallic interface ansi t1.408-1990, integrated services digital netwo rk (isdn) primary rate - customer installation meta llic interfaces layer 1 specification ets 300 011, isdn primary rte user-network interfac e layer 1 specification and test principles, april 1992 ets 300 233, isdn; access digital section for isdn primary rate, may 1994 intel i750, i860, i960 processors and related produ cts data book, 1994 intel 8-bit embedded controllers data book motorola mc68302, integrated multi-protocol process or user's manual 11.1 terminology 11.1.1 nomenclature "transmit" refers to the flow of data from the user interface to the physical line interface. "receive" refers to the flow of data from the physi cal line interface to the user interface. "ingress" refers to the flow of data from the e1 li u's to the sdh interface. "egress" refers to the flow of data from the sdh in terface to the e1 liu's. 11.1.2 signal name prefixes and suffixes the following lists the convention used in this des ign for naming distinguished signals. tx signals pertaining to the ds1 transmit framer rx signals pertaining to the ds1 receive framer li signals pertaining to liu interface module p signals pertaining to microprocessor interface 11.1.3 abbreviations ais alarm indication signal ami alternate mask inversion au administrative unit aug administrative unit group bip bit interleaved parity bpv bipolar violation crc cyclic redundancy check
XRT86SH221 preliminary 341 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 dsn digital signal n (any of ds1, ds1a, ds1c or ds2) dl data link fa frame alignment fas frame alignment signal fcs frame check sequence fifo first in first out fps framing pattern sequence hdlc high level data link control protocol itu the international telecommunications union lapd link access protocol d lcv line code violation liu line interface unit lof loss of frame synchronization lop loss of pointer los loss of signal lte line terminating equipment msoh multiplex section overhead nrz non return to zero oh overhead oof out of frame synchronization oc optical carrier plm payload label mismatch poh path overhead pm performance monitor pmdl path maintenance data link pmon performance monitor pte path terminating equipment rai remote alarm indication rdi remote defect indication rei remote error indication rfi remote failure indication rsoh regenerator section overhead sdh synchronous digital hierarchy rx receive sf super frame sdh synchronous digtial hierarchy spe synchronous payload envelop
preliminary XRT86SH221 342 rev. p1.0.5 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu stm synchronous transport module tu tributary unit tug tributary unit group tx transmit t1dm t1 data multiplexer mp(up) microprocessor vc virtual container vt virtual tributary
XRT86SH221 preliminary 343 sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 ordering information p roduct n umber p ackage t ype o perating t emperature r ange XRT86SH221ib 388 pbga -40c to +85c package dimensions 388 pbga b e 388 ball plastic ball grid array (27 mm x 27 mm, pbga) rev. 1.00 symbol min max min max a 0.067 0.106 1.70 2.70 a1 0.016 0.028 0.40 0.70 a2 0.008 0.028 0.20 0.70 a3 0.039 0.051 1.00 1.30 d 1.055 1.071 26.80 27.20 d1 0.984 bsc 25.00 bsc d2 0.937 0.953 23.80 24.20 b 0.024 0.035 0.60 0.90 e 0.039 bsc 1.00 bsc b 10 20 10 20 inches millimeters note: the control dimension is in millimeter. (a1 corner feature is mfger option)
344 notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar co rporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representa tion that the circuits are free of patent infringement. chart s and schedules contained here in are only for illu stration purposes and may vary depending upon a users speci fic application. while the information in this publ ication has been carefully checked; no responsibility, howe ver, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonabl y be expected to cause failure of the life support system or to significantly affect its safety or effectiveness . products are not authorized for use in such appli cations unless exar corporation receives, in writing, assurances t o its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; (c) potential liability of exar corporation is ad equately protected under the circumstances. copyright 2007 exar corporation datasheet may 2007. all effort hs been made to provide correct informat ion in this data sheet, iif discrepencies are found or more information is required please contact exar applica tion engineering at < ntapplications@exar.com > reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. XRT86SH221 preliminary sdh-to-pdh framer/mapper with integrated 21-channel e1 sh liu rev. p1.0.5 revisions rev. # date description p1.0.0 september 2006 first release of the XRT86SH221 preliminary data sheet. p1.0.1 september 2006 added the application and physi cal interface section. p1.0.2 november 2006 added power consumption numbers, register descriptions, and general edits. p1.0.3 december 2006 updated register information. p1.0.4 march 2007 updated register information, pin d escriptions, and timing diagrams. p1.0.5 may 2007 general edits, updated electrical spe cifications, and clarified register descriptions.

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